u-boot/arch/riscv/cpu
Green Wan c552debbd8 riscv: cpu: fu740: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31 16:35:55 +08:00
..
ax25 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU 2021-03-27 15:04:31 +13:00
fu540 drivers: clk: add fu740 support 2021-05-31 16:35:54 +08:00
fu740 riscv: cpu: fu740: clear feature disable CSR 2021-05-31 16:35:55 +08:00
generic riscv: qemu: Switch to use binman to generate u-boot.itb 2021-05-19 17:01:51 +08:00
cpu.c treewide: Convert macro and uses of __section(foo) to __section("foo") 2021-05-24 14:21:30 -04:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S riscv: cpu: Add callback to init each core 2021-05-05 16:11:22 +08:00
u-boot-spl.lds riscv: Add _image_binary_end for SPL 2020-06-04 09:44:08 +08:00
u-boot.lds riscv: Fix breakage caused by linker relaxation 2020-02-10 14:50:53 +08:00