Yu Chien Peter Lin 8a0d5f2f51 riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode ... The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org>		2023-10-04 18:23:54 +08:00
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cache.c	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
cpu.c	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
Kconfig	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	2023-10-04 18:23:54 +08:00
Makefile	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
spl.c	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00