mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
ab53bd43db
Beacon Embedded has an i.MX8M Plus development kit which consists of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC, and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet PHY. The device trees are already queued for inclusion in Linux 6.3. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
416 lines
9.9 KiB
Text
416 lines
9.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
|
|
*/
|
|
|
|
/ {
|
|
aliases {
|
|
rtc0 = &rtc;
|
|
rtc1 = &snvs_rtc;
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x40000000 0 0xc0000000>,
|
|
<0x1 0x00000000 0 0xc0000000>;
|
|
};
|
|
|
|
reg_wl_bt: regulator-wifi-bt {
|
|
compatible = "regulator-fixed";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_reg_wl_bt>;
|
|
regulator-name = "wl-bt-pow-dwn";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
|
startup-delay-us = <70000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|
|
&A53_0 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_1 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_2 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_3 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&eqos {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_eqos>;
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðphy0>;
|
|
snps,force_thresh_dma_mode;
|
|
status = "okay";
|
|
|
|
mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy0: ethernet-phy@3 {
|
|
compatible = "ethernet-phy-id0022.1640",
|
|
"ethernet-phy-ieee802.3-c22";
|
|
reg = <3>;
|
|
reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&flexspi {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_flexspi0>;
|
|
status = "okay";
|
|
|
|
flash0: flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <80000000>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
clock-frequency = <384000>;
|
|
status = "okay";
|
|
|
|
pmic@25 {
|
|
compatible = "nxp,pca9450c";
|
|
reg = <0x25>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pmic>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
regulators {
|
|
buck1: BUCK1 {
|
|
regulator-name = "BUCK1";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <2187500>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <3125>;
|
|
};
|
|
|
|
buck2: BUCK2 {
|
|
regulator-name = "BUCK2";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <2187500>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <3125>;
|
|
nxp,dvs-run-voltage = <950000>;
|
|
nxp,dvs-standby-voltage = <850000>;
|
|
};
|
|
|
|
buck4: BUCK4 {
|
|
regulator-name = "BUCK4";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck5: BUCK5 {
|
|
regulator-name = "BUCK5";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck6: BUCK6 {
|
|
regulator-name = "BUCK6";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <3400000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo1: LDO1 {
|
|
regulator-name = "LDO1";
|
|
regulator-min-microvolt = <1600000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo3: LDO3 {
|
|
regulator-name = "LDO3";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo4: LDO4 {
|
|
regulator-name = "LDO4";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo5: LDO5 {
|
|
regulator-name = "LDO5";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
clock-frequency = <384000>;
|
|
status = "okay";
|
|
|
|
eeprom@50 {
|
|
compatible = "atmel,24c64";
|
|
reg = <0x50>;
|
|
pagesize = <32>;
|
|
read-only; /* Manufacturing EEPROM programmed at factory */
|
|
};
|
|
|
|
rtc: rtc@51 {
|
|
compatible = "nxp,pcf85263";
|
|
reg = <0x51>;
|
|
};
|
|
};
|
|
|
|
&snvs_pwrkey {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
|
uart-has-rtscts;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
bus-width = <4>;
|
|
vmmc-supply = <®_wl_bt>;
|
|
cap-sd-highspeed;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
keep-power-in-suspend;
|
|
wakeup-source;
|
|
non-removable;
|
|
cap-power-off-card;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
|
|
mwifiex: wifi@1 {
|
|
compatible = "marvell,sd8997";
|
|
reg = <1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wlan>;
|
|
interrupt-parent = <&gpio2>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_eqos: eqosgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
|
|
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
|
|
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
|
|
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
|
|
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
|
|
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
|
|
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
|
|
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
|
|
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
|
|
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
|
|
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
|
|
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
|
|
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
|
|
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
|
|
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
|
|
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexspi0: flexspi0grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
|
|
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
|
|
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
|
|
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
|
|
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
|
|
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
|
|
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
|
|
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_wl_bt: reg-wl-btgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
|
|
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
|
|
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
|
|
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
|
|
>;
|
|
};
|
|
|
|
pinctrl_wlan: wlangrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140
|
|
>;
|
|
};
|
|
};
|