u-boot/arch/riscv/cpu/generic/Kconfig
Heinrich Schuchardt 6aabe229f8 riscv: define a cache line size for the generic CPU
The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
2023-07-24 13:22:24 +08:00

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# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
config GENERIC_RISCV
bool
select BINMAN if SPL
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply RISCV_ACLINT if RISCV_MMODE
imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT