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e4aea57fa7
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC. This is quite rudimentary right now, and only supports applying a default pin configuration as specified by the device tree. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
379 lines
10 KiB
C
379 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014-2018 Renesas Electronics Europe Limited
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*
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* Phil Edworthy <phil.edworthy@renesas.com>
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* Based on a driver originally written by Michel Pollet at Renesas.
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*/
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#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <dm/read.h>
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#include <regmap.h>
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/* Field positions and masks in the pinmux registers */
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#define RZN1_L1_PIN_DRIVE_STRENGTH 10
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#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
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#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
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#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
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#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
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#define RZN1_L1_PIN_PULL 8
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#define RZN1_L1_PIN_PULL_NONE 0
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#define RZN1_L1_PIN_PULL_UP 1
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#define RZN1_L1_PIN_PULL_DOWN 3
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#define RZN1_L1_FUNCTION 0
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#define RZN1_L1_FUNC_MASK 0xf
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#define RZN1_L1_FUNCTION_L2 0xf
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/*
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* The hardware manual describes two levels of multiplexing, but it's more
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* logical to think of the hardware as three levels, with level 3 consisting of
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* the multiplexing for Ethernet MDIO signals.
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*
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* Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
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* that level 2 functions are used instead. Level 2 has a lot more options,
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* going from 0 to 61. Level 3 allows selection of MDIO functions which can be
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* floating, or one of seven internal peripherals. Unfortunately, there are two
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* level 2 functions that can select MDIO, and two MDIO channels so we have four
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* sets of level 3 functions.
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*
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* For this driver, we've compounded the numbers together, so:
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* 0 to 9 is level 1
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* 10 to 71 is 10 + level 2 number
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* 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
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* 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
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* 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
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* 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
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* Examples:
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* Function 28 corresponds UART0
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* Function 73 corresponds to MDIO0 to GMAC0
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*
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* There are 170 configurable pins (called PL_GPIO in the datasheet).
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*/
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/*
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* Structure detailing the HW registers on the RZ/N1 devices.
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* Both the Level 1 mux registers and Level 2 mux registers have the same
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* structure. The only difference is that Level 2 has additional MDIO registers
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* at the end.
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*/
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struct rzn1_pinctrl_regs {
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u32 conf[170];
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u32 pad0[86];
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u32 status_protect; /* 0x400 */
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/* MDIO mux registers, level2 only */
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u32 l2_mdio[2];
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};
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#define NUM_CONF ARRAY_SIZE(((struct rzn1_pinctrl_regs *)0)->conf)
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#define level1_write(map, member, val) \
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regmap_range_set(map, 0, struct rzn1_pinctrl_regs, member, val)
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#define level1_read(map, member, valp) \
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regmap_range_get(map, 0, struct rzn1_pinctrl_regs, member, valp)
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#define level2_write(map, member, val) \
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regmap_range_set(map, 1, struct rzn1_pinctrl_regs, member, val)
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#define level2_read(map, member, valp) \
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regmap_range_get(map, 1, struct rzn1_pinctrl_regs, member, valp)
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/**
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* struct rzn1_pmx_func - describes rzn1 pinmux functions
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* @name: the name of this specific function
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* @groups: corresponding pin groups
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* @num_groups: the number of groups
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*/
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struct rzn1_pmx_func {
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const char *name;
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const char **groups;
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unsigned int num_groups;
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};
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/**
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* struct rzn1_pin_group - describes an rzn1 pin group
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* @name: the name of this specific pin group
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* @func: the name of the function selected by this group
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* @npins: the number of pins in this group array, i.e. the number of
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* elements in .pins so we can iterate over that array
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* @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
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* @pin_ids: array of pin_ids, i.e. the value used to select the mux
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*/
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struct rzn1_pin_group {
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const char *name;
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const char *func;
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unsigned int npins;
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unsigned int *pins;
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u8 *pin_ids;
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};
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struct rzn1_pinctrl {
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struct device *dev;
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struct clk *clk;
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struct pinctrl_dev *pctl;
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u32 lev1_protect_phys;
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u32 lev2_protect_phys;
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int mdio_func[2];
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struct rzn1_pin_group *groups;
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unsigned int ngroups;
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struct rzn1_pmx_func *functions;
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unsigned int nfunctions;
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};
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struct rzn1_pinctrl_priv {
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struct regmap *regmap;
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u32 lev1_protect_phys;
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u32 lev2_protect_phys;
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struct clk *clk;
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};
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enum {
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LOCK_LEVEL1 = 0x1,
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LOCK_LEVEL2 = 0x2,
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LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
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};
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static void rzn1_hw_set_lock(struct rzn1_pinctrl_priv *priv, u8 lock, u8 value)
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{
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/*
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* The pinmux configuration is locked by writing the physical address of
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* the status_protect register to itself. It is unlocked by writing the
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* address | 1.
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*/
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if (lock & LOCK_LEVEL1) {
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u32 val = priv->lev1_protect_phys | !(value & LOCK_LEVEL1);
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level1_write(priv->regmap, status_protect, val);
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}
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if (lock & LOCK_LEVEL2) {
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u32 val = priv->lev2_protect_phys | !(value & LOCK_LEVEL2);
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level2_write(priv->regmap, status_protect, val);
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}
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}
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static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl_priv *priv, int mdio,
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u32 func)
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{
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debug("setting mdio%d to %u\n", mdio, func);
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level2_write(priv->regmap, l2_mdio[mdio], func);
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}
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/*
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* Using a composite pin description, set the hardware pinmux registers
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* with the corresponding values.
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* Make sure to unlock write protection and reset it afterward.
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*
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* NOTE: There is no protection for potential concurrency, it is assumed these
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* calls are serialized already.
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*/
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static int rzn1_set_hw_pin_func(struct rzn1_pinctrl_priv *priv,
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unsigned int pin, unsigned int func)
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{
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u32 l1_cache;
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u32 l2_cache;
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u32 l1;
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u32 l2;
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/* Level 3 MDIO multiplexing */
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if (func >= RZN1_FUNC_MDIO0_HIGHZ &&
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func <= RZN1_FUNC_MDIO1_E1_SWITCH) {
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int mdio_channel;
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u32 mdio_func;
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if (func <= RZN1_FUNC_MDIO1_HIGHZ)
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mdio_channel = 0;
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else
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mdio_channel = 1;
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/* Get MDIO func, and convert the func to the level 2 number */
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if (func <= RZN1_FUNC_MDIO0_SWITCH) {
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mdio_func = func - RZN1_FUNC_MDIO0_HIGHZ;
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func = RZN1_FUNC_ETH_MDIO;
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} else if (func <= RZN1_FUNC_MDIO0_E1_SWITCH) {
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mdio_func = func - RZN1_FUNC_MDIO0_E1_HIGHZ;
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func = RZN1_FUNC_ETH_MDIO_E1;
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} else if (func <= RZN1_FUNC_MDIO1_SWITCH) {
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mdio_func = func - RZN1_FUNC_MDIO1_HIGHZ;
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func = RZN1_FUNC_ETH_MDIO;
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} else {
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mdio_func = func - RZN1_FUNC_MDIO1_E1_HIGHZ;
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func = RZN1_FUNC_ETH_MDIO_E1;
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}
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rzn1_pinctrl_mdio_select(priv, mdio_channel, mdio_func);
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}
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/* Note here, we do not allow anything past the MDIO Mux values */
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if (pin >= NUM_CONF || func >= RZN1_FUNC_MDIO0_HIGHZ)
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return -EINVAL;
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level1_read(priv->regmap, conf[pin], &l1);
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l1_cache = l1;
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level2_read(priv->regmap, conf[pin], &l2);
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l2_cache = l2;
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debug("setting func for pin %u to %u\n", pin, func);
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l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
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if (func < RZN1_FUNC_L2_OFFSET) {
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l1 |= (func << RZN1_L1_FUNCTION);
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} else {
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l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
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l2 = func - RZN1_FUNC_L2_OFFSET;
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}
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/* If either configuration changes, we update both anyway */
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if (l1 != l1_cache || l2 != l2_cache) {
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level1_write(priv->regmap, conf[pin], l1);
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level2_write(priv->regmap, conf[pin], l2);
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}
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return 0;
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}
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static int rzn1_pinconf_set(struct rzn1_pinctrl_priv *priv, unsigned int pin,
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unsigned int bias, unsigned int strength)
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{
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u32 l1, l1_cache;
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u32 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
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level1_read(priv->regmap, conf[pin], &l1);
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l1_cache = l1;
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switch (bias) {
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case PIN_CONFIG_BIAS_PULL_UP:
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debug("set pin %d pull up\n", pin);
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l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
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l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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debug("set pin %d pull down\n", pin);
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l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
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l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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debug("set pin %d bias off\n", pin);
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l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
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l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
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break;
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}
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switch (strength) {
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case 4:
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drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
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break;
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case 6:
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drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
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break;
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case 8:
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drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
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break;
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case 12:
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drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
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break;
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}
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debug("set pin %d drv %umA\n", pin, drv);
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l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
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l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
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if (l1 != l1_cache)
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level1_write(priv->regmap, conf[pin], l1);
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return 0;
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}
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static int rzn1_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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struct rzn1_pinctrl_priv *priv = dev_get_priv(dev);
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int size;
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int ret;
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u32 val;
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u32 bias;
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/* Pullup/down bias, common to all pins in group */
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bias = PIN_CONFIG_BIAS_PULL_UP;
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if (dev_read_bool(config, "bias-disable"))
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bias = PIN_CONFIG_BIAS_DISABLE;
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else if (dev_read_bool(config, "bias-pull-up"))
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bias = PIN_CONFIG_BIAS_PULL_UP;
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else if (dev_read_bool(config, "bias-pull-down"))
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bias = PIN_CONFIG_BIAS_PULL_DOWN;
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/* Drive strength, common to all pins in group */
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u32 strength = dev_read_u32_default(config, "drive-strength", 8);
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/* Number of pins */
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ret = dev_read_size(config, "pinmux");
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if (ret < 0)
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return ret;
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size = ret / sizeof(val);
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for (int i = 0; i < size; i++) {
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ret = dev_read_u32_index(config, "pinmux", i, &val);
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if (ret)
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return ret;
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unsigned int pin = val & 0xff;
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unsigned int func = val >> 8;
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debug("%s pin %d func %d bias %d strength %d\n",
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config->name, pin, func, bias, strength);
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rzn1_hw_set_lock(priv, LOCK_ALL, LOCK_ALL);
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rzn1_set_hw_pin_func(priv, pin, func);
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rzn1_pinconf_set(priv, pin, bias, strength);
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rzn1_hw_set_lock(priv, LOCK_ALL, 0);
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}
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return 0;
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}
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static struct pinctrl_ops rzn1_pinctrl_ops = {
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.set_state = rzn1_pinctrl_set_state,
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};
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static int rzn1_pinctrl_probe(struct udevice *dev)
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{
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struct rzn1_pinctrl_priv *priv = dev_get_priv(dev);
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ofnode node = dev_ofnode(dev);
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int ret;
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ret = regmap_init_mem(node, &priv->regmap);
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if (ret)
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return ret;
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priv->lev1_protect_phys = (u32)regmap_get_range(priv->regmap, 0) +
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offsetof(struct rzn1_pinctrl_regs, status_protect);
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priv->lev2_protect_phys = (u32)regmap_get_range(priv->regmap, 1) +
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offsetof(struct rzn1_pinctrl_regs, status_protect);
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return 0;
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}
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static const struct udevice_id rzn1_pinctrl_ids[] = {
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{ .compatible = "renesas,rzn1-pinctrl", },
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{ },
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};
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U_BOOT_DRIVER(pinctrl_rzn1) = {
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.name = "rzn1-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rzn1_pinctrl_ids,
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.priv_auto = sizeof(struct rzn1_pinctrl_priv),
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.ops = &rzn1_pinctrl_ops,
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.probe = rzn1_pinctrl_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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