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u-boot/arch/riscv/cpu
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Bin Meng 883f553e6b riscv: Optimize source end address calculation in start.S 
The __bss_start is the source end address hence load its address
directly into register 't2' for optimization.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20 20:45:08 +08:00
..
andesv5 riscv: Rename Andes cpu and board names 2023-02-17 19:07:48 +08:00
fu540 board_f: Fix types for board_get_usable_ram_top() 2022-09-23 15:12:42 -04:00
fu740 board_f: Fix types for board_get_usable_ram_top() 2022-09-23 15:12:42 -04:00
generic board_f: Fix types for board_get_usable_ram_top() 2022-09-23 15:12:42 -04:00
jh7110 riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC 2023-04-20 16:08:44 +08:00
cpu.c riscv: cpu: check U-Mode before counteren write 2023-02-01 16:17:13 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S riscv: Optimize source end address calculation in start.S 2023-04-20 20:45:08 +08:00
u-boot-spl.lds linker_lists: Rename sections to remove . prefix 2022-06-23 12:58:18 -04:00
u-boot.lds linker_lists: Rename sections to remove . prefix 2022-06-23 12:58:18 -04:00