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Yu Chien Peter Lin d1b24a6140 riscv: andes: Fix enable register settings of PLICSW 
On 32-core platform, hart31 gets stuck at secondary_hart_loop
as the corresponding enable bit is not set in enable_ipi().
We should program the next word (0x2f84) which is assigned
as the enable register of hart31. It should be done in the same
way when we invoke riscv_send_ipi() to trigger software interrupt
on hart31.

The following diagram shows the enable bits of the fixed PLICSW
scheme.

   Pending regs: 0x1000  x---0---0---0---0------0---0
Pending hart ID:             0   1   2   3 ... 30  31
   Interrupt ID:         0   1   2   3   4 ... 31  32
                         |   |   |   |   |      |   |
    Enable regs: 0x2000  x---1---0---0---0-...--0---0---> hart0
                         |   |   |   |   |      |   |
                 0x2080  x---0---1---0---0-...--0---0---> hart1
                         |   |   |   |   |      |   |
                 0x2100  x---0---0---1---0-...--0---0---> hart2
                         |   |   |   |   |      |   |
                 0x2180  x---0---0---0---1-...--0---0---> hart3
                         .   .   .   .   .      .   .
                         .   .   .   .   .      .   .
                         .   .   .   .   .      .   .
                 0x2f00  x---0---0---0---0-...--1---0---> hart30
                         |   |   |   |   |      |   |
                 0x2f80  x---0---0---0---0-...--0---1---> hart31
                         <-------- word 0 -------><--- word 1 --->

This patch includes some cleanups to macros/functions.

Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy")
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
2023-12-06 16:05:39 +08:00
..
aclint_ipi.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
andes_plicsw.c riscv: andes: Fix enable register settings of PLICSW 2023-12-06 16:05:39 +08:00
asm-offsets.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
boot.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
bootm.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
cache.c riscv: Weakly define invalidate_icache_range() 2023-11-02 15:15:54 +08:00
crt0_riscv_efi.S efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWARE 2022-12-29 10:51:50 +01:00
elf_riscv32_efi.lds efi_loader: fix SectionAlignment, FileAlignment 2022-01-15 10:57:22 +01:00
elf_riscv64_efi.lds efi_loader: fix SectionAlignment, FileAlignment 2022-01-15 10:57:22 +01:00
fdt_fixup.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
image.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
interrupts.c riscv: allow resume after exception 2023-11-02 16:22:06 +08:00
Makefile riscv: Add Zbb support for building U-Boot 2023-10-19 17:29:50 +08:00
memcpy.S riscv: memcpy: check src and dst before copy 2023-02-01 16:17:45 +08:00
memmove.S riscv: Fix memmove and optimise memcpy when misalign 2021-05-17 16:47:33 +08:00
memset.S riscv: assembler versions of memcpy, memmove, memset 2021-04-08 15:37:29 +08:00
reloc_riscv_efi.c riscv: Remove unused _relocate arguments 2018-07-19 16:31:37 -04:00
reset.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
sbi.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
sbi_ipi.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
semihosting.S riscv: semihosting: replace inline assembly with assembly file 2023-03-06 19:24:34 -05:00
setjmp.S riscv: simplify longjmp 2021-04-08 15:37:29 +08:00
sifive_cache.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
smp.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
spl.c riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
strcmp_zbb.S riscv: Add Zbb support for building U-Boot 2023-10-19 17:29:50 +08:00
strlen_zbb.S riscv: Add Zbb support for building U-Boot 2023-10-19 17:29:50 +08:00
strncmp_zbb.S riscv: Add Zbb support for building U-Boot 2023-10-19 17:29:50 +08:00