mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
71d2a5e5ef
Synchronize R-Car device trees with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
The following script has been used for the synchronization:
$ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do
if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then
cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ;
elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then
cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/
else
echo "NOT FOUND: $i"
fi
done
$ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' )
Move the include/dt-bindings/{clk,clock}/versaclock.h header used by
the renesas boards to match Linux 6.1.y as well.
Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used
by the arch/arm/dts/r8a774c0-cat874.dts board.
Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts
from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" .
Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect
the card enumeration in ebisu.dtsi /aliases DT node .
Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to
reflect the card enumeration in ulcb.dtsi /aliases DT node .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
334 lines
6.3 KiB
Text
334 lines
6.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020, Compass Electronics Group, LLC
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/versaclock.h>
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/ {
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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osc_32k: osc_32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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wlan_pwrseq: wlan_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
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clocks = <&osc_32k>;
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clock-names = "ext_clock";
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post-power-on-delay-ms = <80>;
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};
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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rx-internal-delay-ps = <1800>;
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tx-internal-delay-ps = <2000>;
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clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
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clock-names = "fck", "refclk";
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status = "okay";
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id004d.d074",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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interrupt-parent = <&gpio2>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&gpio6 {
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usb-hub-reset-hog {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-hub-reset";
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};
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};
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&hscif0 {
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
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host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
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clocks = <&osc_32k>;
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clock-names = "extclk";
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max-speed = <4000000>;
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};
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};
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&hscif2 {
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status = "okay";
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pinctrl-0 = <&hscif2_pins>;
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pinctrl-names = "default";
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};
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&i2c4 {
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status = "okay";
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clock-frequency = <100000>;
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pca9654: gpio@20 {
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compatible = "onnn,pca9654";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names =
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"i2c4_20_0",
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"wl_reg_on",
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"bt_reg_on",
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"i2c4_20_3",
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"i2c4_20_4",
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"bt_dev_wake",
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"i2c4_20_6",
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"i2c4_20_7";
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};
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pca9654_lte: gpio@21 {
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compatible = "onnn,pca9654";
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reg = <0x21>;
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interrupt-parent = <&gpio5>;
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interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names =
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"i2c4_21_0",
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"zoe_pwr_on",
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"zoe_extint",
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"zoe_reset_n",
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"sara_reset",
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"i2c4_21_5",
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"sara_pwr_off",
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"sara_networking_status";
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};
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eeprom@50 {
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compatible = "microchip,24c64", "atmel,24c64";
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pagesize = <32>;
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read-only; /* Manufacturing EEPROM programmed at factory */
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reg = <0x50>;
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};
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rtc@51 {
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compatible = "nxp,pcf85263";
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reg = <0x51>;
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};
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versaclock5: versaclock_som@6a {
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compatible = "idt,5p49v6965";
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reg = <0x6a>;
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#clock-cells = <1>;
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clocks = <&x304_clk>;
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clock-names = "xin";
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/* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
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assigned-clocks = <&versaclock5 1>,
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<&versaclock5 2>,
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<&versaclock5 3>,
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<&versaclock5 4>;
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assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
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OUT1 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <100>;
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};
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OUT2 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <100>;
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};
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OUT3 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <100>;
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};
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OUT4 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <3300000>;
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idt,slew-percent = <100>;
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};
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};
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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avb_pins: avb {
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mux {
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groups = "avb_link", "avb_mdio", "avb_mii";
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function = "avb";
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};
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pins_mdio {
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groups = "avb_mdio";
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drive-strength = <24>;
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};
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pins_mii_tx {
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pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
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"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
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drive-strength = <12>;
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};
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};
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scif2_pins: scif2 {
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groups = "scif2_data_a";
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function = "scif2";
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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hscif1_pins: hscif1 {
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groups = "hscif1_data_a", "hscif1_ctrl_a";
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function = "hscif1";
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};
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hscif2_pins: hscif2 {
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groups = "hscif2_data_a";
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function = "hscif2";
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};
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif5_pins: scif5 {
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groups = "scif5_data_a";
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function = "scif5";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk_a";
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function = "scif_clk";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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sdhi2_pins: sd2 {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <1800>;
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};
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sdhi3_pins: sd3 {
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groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
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function = "sdhi3";
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power-source = <1800>;
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};
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};
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&scif_clk {
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clock-frequency = <14745600>;
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdhi2_pins>;
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bus-width = <4>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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non-removable;
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cap-power-off-card;
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keep-power-in-suspend;
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mmc-pwrseq = <&wlan_pwrseq>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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brcmf: bcrmf@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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interrupt-parent = <&gpio1>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "host-wake";
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};
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};
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&sdhi3 {
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pinctrl-0 = <&sdhi3_pins>;
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pinctrl-1 = <&sdhi3_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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fixed-emmc-driver-type = <1>;
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status = "okay";
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};
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&usb2_clksel {
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
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<&versaclock5 3>, <&usb3s0_clk>;
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status = "okay";
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};
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&usb3s0_clk {
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clock-frequency = <100000000>;
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};
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