u-boot/arch/riscv/cpu
Bin Meng 84dc9d2690 riscv: Merge unnecessary SMP ifdefs in start.S
Two consecutive SMP ifdefs blocks can be combined into one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
..
ax25 riscv: ax25: cache: Remove SPL_RISCV_MMODE config check 2020-04-23 10:13:23 +08:00
generic riscv: qemu: Remove the simple-bus driver for the SoC node 2020-04-23 10:14:06 +08:00
cpu.c riscv: add run mode configuration for SPL 2019-08-26 16:07:42 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S riscv: Merge unnecessary SMP ifdefs in start.S 2020-04-23 10:14:06 +08:00
u-boot-spl.lds riscv: Fix clear bss loop in the start-up code 2019-12-10 08:23:10 +08:00
u-boot.lds riscv: Fix breakage caused by linker relaxation 2020-02-10 14:50:53 +08:00