mirror of
https://github.com/AsahiLinux/u-boot
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e053ccf6ef
This patch adds general board files based on MT7981 SoCs. MT7981 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller are also shared with spi controller. So three configs are need for these boot types: 1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND 2. mt7981_emmc_rfb_defconfig - eMMC only 3. mt7981_sd_rfb_defconfig - SD only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
173 lines
2.8 KiB
Text
173 lines
2.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7981.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "mt7981-rfb";
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compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
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chosen {
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stdout-path = &uart0;
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tick-timer = &timer0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "sgmii";
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mediatek,switch = "mt7531";
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reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&pinctrl {
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spi_flash_pins: spi0-pins-func-1 {
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mux {
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function = "flash";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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spi2_flash_pins: spi2-spi2-pins {
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mux {
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function = "spi";
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groups = "spi2", "spi2_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
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};
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};
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spic_pins: spi1-pins-func-1 {
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mux {
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function = "spi";
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groups = "spi1_1";
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};
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};
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uart1_pins: spi1-pins-func-3 {
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mux {
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function = "uart";
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groups = "uart1_2";
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};
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};
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/* pin15 as pwm0 */
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one_pwm_pins: one-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1";
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};
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};
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/* pin15 as pwm0 and pin14 as pwm1 */
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two_pwm_pins: two-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0";
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};
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};
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/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
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three_pwm_pins: three-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0", "pwm2";
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};
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};
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};
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&spi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_flash_pins>;
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status = "okay";
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must_tx;
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enhance_timing;
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dma_ext;
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ipm_design;
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support_quad;
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tick_dly = <2>;
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sample_sel = <0>;
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spi_nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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};
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};
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&spi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_flash_pins>;
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status = "okay";
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must_tx;
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enhance_timing;
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dma_ext;
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ipm_design;
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support_quad;
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tick_dly = <2>;
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sample_sel = <0>;
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spi_nor@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <52000000>;
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&two_pwm_pins>;
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status = "okay";
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};
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&watchdog {
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status = "disabled";
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};
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