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814e1a4b8c
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> |
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base.h | ||
gpio.h | ||
mbox.h | ||
msg.h | ||
sdhci.h | ||
timer.h | ||
wdog.h |