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u-boot/arch/arm/cpu/armv7/omap-common
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Lokesh Vutla 802bb57a58 ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value 
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-02-16 12:41:40 -05:00
..
abb.c replace DIV_ROUND with DIV_ROUND_CLOSEST 2014-11-20 11:28:25 -05:00
boot-common.c TI ARMv7: Don't use GD before crt0.S has set it 2015-01-16 14:52:52 -05:00
clocks-common.c ARM: OMAP5: DRA7xx: Add support for power rail grouping 2015-01-29 12:00:49 -05:00
emif-common.c ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value 2015-02-16 12:41:40 -05:00
hwinit-common.c TI ARMv7: Don't use GD before crt0.S has set it 2015-01-16 14:52:52 -05:00
lowlevel_init.S Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
Makefile am33xx/omap: Allow cache enable for all Sitara/OMAP 2014-06-11 16:25:39 -04:00
mem-common.c ARM: omap: clean redundant PISMO_xx macros used in OMAP3 2014-07-25 16:26:12 -04:00
omap-cache.c am33xx/omap: Allow cache enable for all Sitara/OMAP 2014-06-11 16:25:39 -04:00
pipe3-phy.c ARM: OMAP5: Add Pipe3 PHY driver 2013-12-04 08:12:08 -05:00
pipe3-phy.h ARM: OMAP5: Add Pipe3 PHY driver 2013-12-04 08:12:08 -05:00
reset.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
sata.c OMAP5+: sata/scsi: implement scsi_bus_reset() 2015-01-05 15:13:46 -05:00
timer.c omap-common/hwinit-common.c: timer_init() doesn't need to touch gd 2015-01-05 15:13:45 -05:00
u-boot-spl.lds arm: Add missing .vectors section to linker scripts 2014-08-30 07:46:41 -04:00
utils.c OMAP: common: consolidate fake USB ethernet MAC address creation 2014-04-17 14:39:54 -04:00
vc.c ARM: OMAP4+: pmic: Make generic bus init and write functions 2013-06-10 08:43:09 -04:00