Stefan Roese 07b7b0037a [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup ... As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>		2007-03-06 07:47:04 +01:00
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board/amcc/sequoia	[PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup	2007-03-06 07:47:04 +01:00
nand_boot.c	Coding style cleanup	2006-10-09 00:42:01 +02:00