Pragnesh Patel 7c45fc9870 riscv: cpu: fu540: Add support for cpu fu540 ... Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>		2020-06-04 09:44:09 +08:00
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ax25	common: Drop net.h from common header	2020-05-18 17:33:31 -04:00
fu540	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
generic	common: Drop net.h from common header	2020-05-18 17:33:31 -04:00
cpu.c	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: Provide a mechanism to fix DT for reserved memory	2020-04-23 10:14:16 +08:00
u-boot-spl.lds	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00