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0caac5f415
By default, on Pantheon SoC DCache Lnd ICache line lengths are 32 bytes long Signed-off-by: Lei Wen <leiwen@marvell.com>
70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _PANTHEON_CONFIG_H
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#define _PANTHEON_CONFIG_H
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#include <asm/arch/pantheon.h>
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#define CONFIG_ARM926EJS 1 /* Basic Architecture */
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/* default Dcache Line length for pantheon */
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
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#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
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#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
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#define MV_MFPR_BASE PANTHEON_MFPR_BASE
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#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE
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#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
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represents UART Unit Enable */
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/*
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* I2C definition
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*/
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_I2C_MV 1
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#define CONFIG_MV_I2C_REG 0xd4011000
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 0
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#define CONFIG_SYS_I2C_SLAVE 0xfe
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#endif
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/*
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* MMC definition
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_CMD_FAT 1
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#define CONFIG_MMC 1
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_SDHCI 1
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#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
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#define CONFIG_MMC_SDMA 1
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#define CONFIG_MV_SDHCI 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_EFI_PARTITION 1
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#define CONFIG_SYS_MMC_NUM 2
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#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000}
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#endif
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#endif /* _PANTHEON_CONFIG_H */
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