u-boot/arch/arm
Fabio Estevam 76c91e668a mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.

Comparing the watchdog behaviour on a revB versus revC board:

- On a mx6qsabresd revB:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...

- On a mx6qsabresd revC:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR

So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.

Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-02-12 13:54:34 +01:00
..
cpu mx6: Disable Power Down Bit of watchdog 2013-02-12 13:54:34 +01:00
dts EXYNOS5: Add device node for USB. 2013-01-08 21:14:34 +09:00
imx-common imximage.cfg: run files through C preprocessor 2013-01-22 10:20:13 +01:00
include/asm mx6: Disable Power Down Bit of watchdog 2013-02-12 13:54:34 +01:00
lib arm: Tabify code for MMC initialization 2013-01-10 22:28:36 +01:00
config.mk arm: work around assembler bug 2012-10-04 14:19:04 +02:00