Michal Simek 7576ab2fac riscv: Add support for AMD/Xilinx MicroBlaze V ... MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>		2023-12-18 11:08:49 +08:00
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cpu	riscv: Align the trap handler to 64 bytes	2023-11-02 15:15:46 +08:00
dts	riscv: Add support for AMD/Xilinx MicroBlaze V	2023-12-18 11:08:49 +08:00
include/asm	riscv: io.h: Fix signatures of reads/writes functions	2023-11-28 16:19:06 -05:00
lib	riscv: allow resume after exception	2023-11-02 16:22:06 +08:00
config.mk	riscv: Support CONFIG_REMAKE_ELF	2023-04-20 20:45:08 +08:00
Kconfig	riscv: Add support for AMD/Xilinx MicroBlaze V	2023-12-18 11:08:49 +08:00
Makefile	riscv: Add Zbb support for building U-Boot	2023-10-19 17:29:50 +08:00