mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
71d2a5e5ef
Synchronize R-Car device trees with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
The following script has been used for the synchronization:
$ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do
if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then
cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ;
elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then
cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/
else
echo "NOT FOUND: $i"
fi
done
$ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' )
Move the include/dt-bindings/{clk,clock}/versaclock.h header used by
the renesas boards to match Linux 6.1.y as well.
Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used
by the arch/arm/dts/r8a774c0-cat874.dts board.
Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts
from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" .
Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect
the card enumeration in ebisu.dtsi /aliases DT node .
Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to
reflect the card enumeration in ulcb.dtsi /aliases DT node .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
1220 lines
33 KiB
Text
1220 lines
33 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the R-Car V3M (R8A77970) SoC
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*
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* Copyright (C) 2016-2017 Renesas Electronics Corp.
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* Copyright (C) 2017 Cogent Embedded, Inc.
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*/
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#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/r8a77970-sysc.h>
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/ {
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compatible = "renesas,r8a77970";
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#address-cells = <2>;
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#size-cells = <2>;
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
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power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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};
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a53_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <1>;
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clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
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power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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};
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L2_CA53: cache-controller {
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compatible = "cache";
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power-domains = <&sysc R8A77970_PD_CA53_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a53_0>, <&a53_1>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a77970-wdt",
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"renesas,rcar-gen3-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 402>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 402>;
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status = "disabled";
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77970",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 22>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 912>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a77970",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 28>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 911>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a77970",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 910>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a77970",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 909>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a77970",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 6>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 908>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a77970",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 15>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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};
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pfc: pinctrl@e6060000 {
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compatible = "renesas,pfc-r8a77970";
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reg = <0 0xe6060000 0 0x504>;
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};
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cmt0: timer@e60f0000 {
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compatible = "renesas,r8a77970-cmt0",
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"renesas,rcar-gen3-cmt0";
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reg = <0 0xe60f0000 0 0x1004>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 303>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 303>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,r8a77970-cmt1",
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"renesas,rcar-gen3-cmt1";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 302>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 302>;
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status = "disabled";
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};
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cmt2: timer@e6140000 {
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compatible = "renesas,r8a77970-cmt1",
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"renesas,rcar-gen3-cmt1";
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reg = <0 0xe6140000 0 0x1004>;
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 301>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 301>;
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status = "disabled";
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};
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cmt3: timer@e6148000 {
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compatible = "renesas,r8a77970-cmt1",
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"renesas,rcar-gen3-cmt1";
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reg = <0 0xe6148000 0 0x1004>;
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interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 300>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 300>;
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status = "disabled";
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77970-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77970-rst";
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reg = <0 0xe6160000 0 0x200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77970-sysc";
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reg = <0 0xe6180000 0 0x440>;
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#power-domain-cells = <1>;
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};
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thermal: thermal@e6190000 {
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compatible = "renesas,thermal-r8a77970";
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reg = <0 0xe6190000 0 0x10>,
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<0 0xe6190100 0 0x120>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 522>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 522>;
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#thermal-sensor-cells = <0>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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tmu0: timer@e61e0000 {
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compatible = "renesas,tmu-r8a77970", "renesas,tmu";
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reg = <0 0xe61e0000 0 0x30>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 125>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 125>;
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status = "disabled";
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};
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tmu1: timer@e6fc0000 {
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compatible = "renesas,tmu-r8a77970", "renesas,tmu";
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reg = <0 0xe6fc0000 0 0x30>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 124>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 124>;
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status = "disabled";
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};
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tmu2: timer@e6fd0000 {
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compatible = "renesas,tmu-r8a77970", "renesas,tmu";
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reg = <0 0xe6fd0000 0 0x30>;
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interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 123>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 123>;
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status = "disabled";
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};
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tmu3: timer@e6fe0000 {
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compatible = "renesas,tmu-r8a77970", "renesas,tmu";
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reg = <0 0xe6fe0000 0 0x30>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 122>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 122>;
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status = "disabled";
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};
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tmu4: timer@ffc00000 {
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compatible = "renesas,tmu-r8a77970", "renesas,tmu";
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reg = <0 0xffc00000 0 0x30>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 121>;
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clock-names = "fck";
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 121>;
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status = "disabled";
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};
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i2c0: i2c@e6500000 {
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compatible = "renesas,i2c-r8a77970",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe6500000 0 0x40>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 931>;
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power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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resets = <&cpg 931>;
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dmas = <&dmac1 0x91>, <&dmac1 0x90>,
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<&dmac2 0x91>, <&dmac2 0x90>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6508000 {
|
|
compatible = "renesas,i2c-r8a77970",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 930>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 930>;
|
|
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
|
|
<&dmac2 0x93>, <&dmac2 0x92>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6510000 {
|
|
compatible = "renesas,i2c-r8a77970",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe6510000 0 0x40>;
|
|
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 929>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 929>;
|
|
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
|
|
<&dmac2 0x95>, <&dmac2 0x94>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e66d0000 {
|
|
compatible = "renesas,i2c-r8a77970",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe66d0000 0 0x40>;
|
|
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 928>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 928>;
|
|
dmas = <&dmac1 0x97>, <&dmac1 0x96>,
|
|
<&dmac2 0x97>, <&dmac2 0x96>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@e66d8000 {
|
|
compatible = "renesas,i2c-r8a77970",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe66d8000 0 0x40>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 927>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 927>;
|
|
dmas = <&dmac1 0x99>, <&dmac1 0x98>,
|
|
<&dmac2 0x99>, <&dmac2 0x98>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e6540000 {
|
|
compatible = "renesas,hscif-r8a77970",
|
|
"renesas,rcar-gen3-hscif",
|
|
"renesas,hscif";
|
|
reg = <0 0xe6540000 0 96>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 520>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
|
|
<&dmac2 0x31>, <&dmac2 0x30>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 520>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e6550000 {
|
|
compatible = "renesas,hscif-r8a77970",
|
|
"renesas,rcar-gen3-hscif",
|
|
"renesas,hscif";
|
|
reg = <0 0xe6550000 0 96>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 519>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
|
|
<&dmac2 0x33>, <&dmac2 0x32>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 519>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e6560000 {
|
|
compatible = "renesas,hscif-r8a77970",
|
|
"renesas,rcar-gen3-hscif",
|
|
"renesas,hscif";
|
|
reg = <0 0xe6560000 0 96>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 518>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
|
|
<&dmac2 0x35>, <&dmac2 0x34>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 518>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif3: serial@e66a0000 {
|
|
compatible = "renesas,hscif-r8a77970",
|
|
"renesas,rcar-gen3-hscif", "renesas,hscif";
|
|
reg = <0 0xe66a0000 0 96>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 517>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
|
|
<&dmac2 0x37>, <&dmac2 0x36>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 517>;
|
|
status = "disabled";
|
|
};
|
|
|
|
canfd: can@e66c0000 {
|
|
compatible = "renesas,r8a77970-canfd",
|
|
"renesas,rcar-gen3-canfd";
|
|
reg = <0 0xe66c0000 0 0x8000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch_int", "g_int";
|
|
clocks = <&cpg CPG_MOD 914>,
|
|
<&cpg CPG_CORE R8A77970_CLK_CANFD>,
|
|
<&can_clk>;
|
|
clock-names = "fck", "canfd", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
|
|
assigned-clock-rates = <40000000>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 914>;
|
|
status = "disabled";
|
|
|
|
channel0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel1 {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
avb: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a77970",
|
|
"renesas,etheravb-rcar-gen3";
|
|
reg = <0 0xe6800000 0 0x800>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 812>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 812>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_rt 3>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@e6e30000 {
|
|
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e30000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@e6e31000 {
|
|
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e31000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@e6e32000 {
|
|
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e32000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@e6e33000 {
|
|
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e33000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@e6e34000 {
|
|
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e34000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a77970",
|
|
"renesas,rcar-gen3-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 207>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
|
<&dmac2 0x51>, <&dmac2 0x50>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 207>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a77970",
|
|
"renesas,rcar-gen3-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 206>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
|
<&dmac2 0x53>, <&dmac2 0x52>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 206>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a77970",
|
|
"renesas,rcar-gen3-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 204>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
|
|
<&dmac2 0x57>, <&dmac2 0x56>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 204>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a77970",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 203>,
|
|
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
|
|
<&dmac2 0x59>, <&dmac2 0x58>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 203>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpu: pwm@e6e80000 {
|
|
compatible = "renesas,tpu-r8a77970", "renesas,tpu";
|
|
reg = <0 0xe6e80000 0 0x148>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 304>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 304>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a77970",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6e90000 0 0x64>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 211>;
|
|
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
|
<&dmac2 0x41>, <&dmac2 0x40>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a77970",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6ea0000 0 0x0064>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 210>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 210>;
|
|
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
|
<&dmac2 0x43>, <&dmac2 0x42>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a77970",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c00000 0 0x0064>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 209>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 209>;
|
|
dmas = <&dmac1 0x45>, <&dmac1 0x44>,
|
|
<&dmac2 0x45>, <&dmac2 0x44>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a77970",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c10000 0 0x0064>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 208>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 208>;
|
|
dmas = <&dmac1 0x47>, <&dmac1 0x46>,
|
|
<&dmac2 0x47>, <&dmac2 0x46>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin0: video@e6ef0000 {
|
|
compatible = "renesas,vin-r8a77970";
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 811>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 811>;
|
|
renesas,id = <0>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
vin0csi40: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&csi40vin0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin1: video@e6ef1000 {
|
|
compatible = "renesas,vin-r8a77970";
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 810>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 810>;
|
|
renesas,id = <1>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
vin1csi40: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&csi40vin1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin2: video@e6ef2000 {
|
|
compatible = "renesas,vin-r8a77970";
|
|
reg = <0 0xe6ef2000 0 0x1000>;
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 809>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 809>;
|
|
renesas,id = <2>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
vin2csi40: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&csi40vin2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin3: video@e6ef3000 {
|
|
compatible = "renesas,vin-r8a77970";
|
|
reg = <0 0xe6ef3000 0 0x1000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 808>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 808>;
|
|
renesas,id = <3>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
vin3csi40: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&csi40vin3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dmac1: dma-controller@e7300000 {
|
|
compatible = "renesas,dmac-r8a77970",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe7300000 0 0x10000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7";
|
|
clocks = <&cpg CPG_MOD 218>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 218>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <8>;
|
|
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
|
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
|
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
|
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
|
|
};
|
|
|
|
dmac2: dma-controller@e7310000 {
|
|
compatible = "renesas,dmac-r8a77970",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe7310000 0 0x10000>;
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7";
|
|
clocks = <&cpg CPG_MOD 217>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 217>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <8>;
|
|
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
|
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
|
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
|
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
|
};
|
|
|
|
ipmmu_ds1: iommu@e7740000 {
|
|
compatible = "renesas,ipmmu-r8a77970";
|
|
reg = <0 0xe7740000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ir: iommu@ff8b0000 {
|
|
compatible = "renesas,ipmmu-r8a77970";
|
|
reg = <0 0xff8b0000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
|
power-domains = <&sysc R8A77970_PD_A3IR>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mm: iommu@e67b0000 {
|
|
compatible = "renesas,ipmmu-r8a77970";
|
|
reg = <0 0xe67b0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_rt: iommu@ffc80000 {
|
|
compatible = "renesas,ipmmu-r8a77970";
|
|
reg = <0 0xffc80000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vi0: iommu@febd0000 {
|
|
compatible = "renesas,ipmmu-r8a77970";
|
|
reg = <0 0xfebd0000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
mmc0: mmc@ee140000 {
|
|
compatible = "renesas,sdhi-r8a77970",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 314>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 314>;
|
|
max-frequency = <200000000>;
|
|
iommus = <&ipmmu_ds1 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rpc: spi@ee200000 {
|
|
compatible = "renesas,r8a77970-rpc-if",
|
|
"renesas,rcar-gen3-rpc-if";
|
|
reg = <0 0xee200000 0 0x200>,
|
|
<0 0x08000000 0 0x4000000>,
|
|
<0 0xee208000 0 0x100>;
|
|
reg-names = "regs", "dirmap", "wbuf";
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@f1010000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0 0xf1010000 0 0x1000>,
|
|
<0 0xf1020000 0 0x20000>,
|
|
<0 0xf1040000 0 0x20000>,
|
|
<0 0xf1060000 0 0x20000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
|
IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&cpg CPG_MOD 408>;
|
|
clock-names = "clk";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 408>;
|
|
};
|
|
|
|
vspd0: vsp@fea20000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea20000 0 0x5000>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 623>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 623>;
|
|
renesas,fcp = <&fcpvd0>;
|
|
};
|
|
|
|
fcpvd0: fcp@fea27000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea27000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 603>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 603>;
|
|
};
|
|
|
|
csi40: csi2@feaa0000 {
|
|
compatible = "renesas,r8a77970-csi2";
|
|
reg = <0 0xfeaa0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 716>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 716>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
csi40vin0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vin0csi40>;
|
|
};
|
|
csi40vin1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&vin1csi40>;
|
|
};
|
|
csi40vin2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&vin2csi40>;
|
|
};
|
|
csi40vin3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&vin3csi40>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a77970";
|
|
reg = <0 0xfeb00000 0 0x80000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 724>;
|
|
clock-names = "du.0";
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 724>;
|
|
reset-names = "du.0";
|
|
renesas,vsps = <&vspd0 0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_lvds0: endpoint {
|
|
remote-endpoint = <&lvds0_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds0: lvds-encoder@feb90000 {
|
|
compatible = "renesas,r8a77970-lvds";
|
|
reg = <0 0xfeb90000 0 0x14>;
|
|
clocks = <&cpg CPG_MOD 727>;
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
resets = <&cpg 727>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
lvds0_in: endpoint {
|
|
remote-endpoint =
|
|
<&du_out_lvds0>;
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
prr: chipid@fff00044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xfff00044 0 4>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&thermal>;
|
|
|
|
cooling-maps {
|
|
};
|
|
|
|
trips {
|
|
cpu-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|