Atish Patra d4ea649f17 riscv: Provide a mechanism to fix DT for reserved memory ... In RISC-V, M-mode software can reserve physical memory regions by setting appropriate physical memory protection (PMP) csr. As the PMP csr are accessible only in M-mode, S-mode U-Boot can not read this configuration directly. However, M-mode software can pass this information via reserved-memory node in device tree so that S-mode software can access this information. This patch provides a framework to copy to the reserved-memory node from one DT to another. This will be used to update the DT used by U-Boot and the DT passed to the next stage OS. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>		2020-04-23 10:14:16 +08:00
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ax25	riscv: ax25: cache: Remove SPL_RISCV_MMODE config check	2020-04-23 10:13:23 +08:00
generic	riscv: qemu: Remove the simple-bus driver for the SoC node	2020-04-23 10:14:06 +08:00
cpu.c	riscv: add run mode configuration for SPL	2019-08-26 16:07:42 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: Provide a mechanism to fix DT for reserved memory	2020-04-23 10:14:16 +08:00
u-boot-spl.lds	riscv: Fix clear bss loop in the start-up code	2019-12-10 08:23:10 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00