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https://github.com/AsahiLinux/u-boot
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444ab3569b
The introduction of the DM pinctrl driver made its probe function enable all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device. So far we didn't describe those clocks in our clock driver. As we enable them already in the SPL, the devices happen to work, but the clock driver still complains about not finding those clocks: ========= sunxi_set_gate: (CLK#58) unhandled ========= Add the one-liners that are needed to announce the gate bit for those clocks, to silence that message on the console. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate a10_gates[] = {
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[CLK_AHB_OTG] = GATE(0x060, BIT(0)),
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[CLK_AHB_EHCI0] = GATE(0x060, BIT(1)),
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[CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
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[CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
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[CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
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[CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
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[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
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[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
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[CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
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[CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
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[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
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[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
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[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
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[CLK_AHB_SPI3] = GATE(0x060, BIT(23)),
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[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
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[CLK_APB0_PIO] = GATE(0x068, BIT(5)),
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[CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
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[CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
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[CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
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[CLK_APB1_I2C3] = GATE(0x06c, BIT(3)),
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[CLK_APB1_I2C4] = GATE(0x06c, BIT(15)),
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[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
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[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
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[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
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[CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
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[CLK_APB1_UART4] = GATE(0x06c, BIT(20)),
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[CLK_APB1_UART5] = GATE(0x06c, BIT(21)),
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[CLK_APB1_UART6] = GATE(0x06c, BIT(22)),
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[CLK_APB1_UART7] = GATE(0x06c, BIT(23)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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[CLK_SPI2] = GATE(0x0a8, BIT(31)),
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[CLK_USB_OHCI0] = GATE(0x0cc, BIT(6)),
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[CLK_USB_OHCI1] = GATE(0x0cc, BIT(7)),
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[CLK_USB_PHY] = GATE(0x0cc, BIT(8)),
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[CLK_SPI3] = GATE(0x0d4, BIT(31)),
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};
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static struct ccu_reset a10_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
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[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
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};
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static const struct ccu_desc a10_ccu_desc = {
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.gates = a10_gates,
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.resets = a10_resets,
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};
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static int a10_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
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}
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static const struct udevice_id a10_ccu_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-ccu",
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.data = (ulong)&a10_ccu_desc },
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{ .compatible = "allwinner,sun7i-a20-ccu",
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.data = (ulong)&a10_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun4i_a10) = {
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.name = "sun4i_a10_ccu",
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.id = UCLASS_CLK,
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.of_match = a10_ccu_ids,
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.priv_auto = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = a10_clk_bind,
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};
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