mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
ffefc72083
Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
568 lines
14 KiB
Text
568 lines
14 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include <dt-bindings/mux/ti-serdes.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/leds/common.h>
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#include "k3-am642.dtsi"
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/ {
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compatible = "ti,am642-sk", "ti,am642";
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model = "Texas Instruments AM642 SK";
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
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};
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memory@80000000 {
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device_type = "memory";
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/* 2G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: ipc-memories@a5000000 {
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reg = <0x00 0xa5000000 0x00 0x00800000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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vusb_main: fixed-regulator-vusb-main5v0 {
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/* USB MAIN INPUT 5V DC */
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compatible = "regulator-fixed";
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regulator-name = "vusb_main5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
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/* output of LP8733xx */
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_sys";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vusb_main>;
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regulator-always-on;
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regulator-boot-on;
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};
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vdd_mmc1: fixed-regulator-sd {
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/* TPS2051BD */
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compatible = "regulator-fixed";
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regulator-name = "vdd_mmc1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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enable-active-high;
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vin-supply = <&vcc_3v3_sys>;
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gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
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};
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com8_ls_en: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "com8_ls_en";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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pinctrl-0 = <&main_com8_ls_en_pins_default>;
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pinctrl-names = "default";
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gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
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};
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wlan_en: regulator-2 {
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/* output of SN74AVC4T245RSVR */
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compatible = "regulator-fixed";
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regulator-name = "wlan_en";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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pinctrl-0 = <&main_wlan_en_pins_default>;
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pinctrl-names = "default";
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vin-supply = <&com8_ls_en>;
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gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
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};
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led-controller {
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compatible = "gpio-leds";
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led-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <1>;
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gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-1 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <2>;
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gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-2 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <3>;
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gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-3 {
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <4>;
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gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-4 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <5>;
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gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-5 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <6>;
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gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-6 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <7>;
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gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-7 {
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_HEARTBEAT;
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function-enumerator = <8>;
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linux,default-trigger = "heartbeat";
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gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&main_pmx0 {
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
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AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
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AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
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AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
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AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
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AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
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AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
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AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
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>;
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};
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main_uart0_pins_default: main-uart0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
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AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
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AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
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AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
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>;
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};
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main_usb0_pins_default: main-usb0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
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>;
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};
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main_i2c1_pins_default: main-i2c1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
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AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
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>;
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};
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mdio1_pins_default: mdio1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
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AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
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>;
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};
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rgmii1_pins_default: rgmii1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
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AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
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AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
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AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
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AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
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AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
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AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
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AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
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AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
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AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
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AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
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AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
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>;
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};
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rgmii2_pins_default: rgmii2-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
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AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
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AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
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AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
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AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
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AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
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AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
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AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
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AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
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AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
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AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
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>;
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};
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ospi0_pins_default: ospi0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
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AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
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AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
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AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
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AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
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AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
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AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
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AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
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AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
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AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
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AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
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>;
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};
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main_ecap0_pins_default: main-ecap0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
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>;
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};
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main_wlan_en_pins_default: main-wlan-en-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
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>;
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};
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main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
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>;
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};
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main_wlan_pins_default: main-wlan-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
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>;
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};
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};
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&main_uart0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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};
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&main_uart1 {
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/* main_uart1 is reserved for firmware usage */
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status = "reserved";
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};
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&main_i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c1_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@70 {
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compatible = "nxp,pca9538";
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reg = <0x70>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
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"PRU_DETECT", "MMC1_SD_EN",
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"VPP_LDO_EN", "RPI_PS_3V3_En",
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"RPI_PS_5V0_En", "RPI_HAT_DETECT";
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};
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exp2: gpio@60 {
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compatible = "ti,tpic2810";
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reg = <0x60>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
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};
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};
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/* mcu_gpio0 is reserved for mcu firmware usage */
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&mcu_gpio0 {
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status = "reserved";
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};
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&sdhci0 {
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vmmc-supply = <&wlan_en>;
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bus-width = <4>;
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non-removable;
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cap-power-off-card;
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keep-power-in-suspend;
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ti,driver-strength-ohm = <50>;
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#address-cells = <1>;
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#size-cells = <0>;
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wlcore: wlcore@2 {
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compatible = "ti,wl1837";
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reg = <2>;
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pinctrl-0 = <&main_wlan_pins_default>;
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pinctrl-names = "default";
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interrupt-parent = <&main_gpio0>;
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interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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&sdhci1 {
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/* SD/MMC */
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vmmc-supply = <&vdd_mmc1>;
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pinctrl-names = "default";
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bus-width = <4>;
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pinctrl-0 = <&main_mmc1_pins_default>;
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ti,driver-strength-ohm = <50>;
|
|
disable-wp;
|
|
};
|
|
|
|
&serdes_ln_ctrl {
|
|
idle-states = <AM64_SERDES0_LANE0_USB>;
|
|
};
|
|
|
|
&serdes0 {
|
|
serdes0_usb_link: phy@0 {
|
|
reg = <0>;
|
|
cdns,num-lanes = <1>;
|
|
#phy-cells = <0>;
|
|
cdns,phy-type = <PHY_TYPE_USB3>;
|
|
resets = <&serdes_wiz0 1>;
|
|
};
|
|
};
|
|
|
|
&usbss0 {
|
|
ti,vbus-divider;
|
|
};
|
|
|
|
&usb0 {
|
|
dr_mode = "host";
|
|
maximum-speed = "super-speed";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_usb0_pins_default>;
|
|
phys = <&serdes0_usb_link>;
|
|
phy-names = "cdns3,usb3-phy";
|
|
};
|
|
|
|
&cpsw3g {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&rgmii1_pins_default
|
|
&rgmii2_pins_default>;
|
|
};
|
|
|
|
&cpsw_port1 {
|
|
phy-mode = "rgmii-rxid";
|
|
phy-handle = <&cpsw3g_phy0>;
|
|
};
|
|
|
|
&cpsw_port2 {
|
|
phy-mode = "rgmii-rxid";
|
|
phy-handle = <&cpsw3g_phy1>;
|
|
};
|
|
|
|
&cpsw3g_mdio {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mdio1_pins_default>;
|
|
|
|
cpsw3g_phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
};
|
|
|
|
cpsw3g_phy1: ethernet-phy@1 {
|
|
reg = <1>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
};
|
|
};
|
|
|
|
&tscadc0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&ospi0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ospi0_pins_default>;
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <8>;
|
|
spi-rx-bus-width = <8>;
|
|
spi-max-frequency = <25000000>;
|
|
cdns,tshsl-ns = <60>;
|
|
cdns,tsd2d-ns = <60>;
|
|
cdns,tchsh-ns = <60>;
|
|
cdns,tslch-ns = <60>;
|
|
cdns,read-delay = <4>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster2 {
|
|
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
|
ti,mbox-rx = <0 0 2>;
|
|
ti,mbox-tx = <1 0 2>;
|
|
};
|
|
|
|
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
|
ti,mbox-rx = <2 0 2>;
|
|
ti,mbox-tx = <3 0 2>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster3 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster4 {
|
|
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
|
ti,mbox-rx = <0 0 2>;
|
|
ti,mbox-tx = <1 0 2>;
|
|
};
|
|
|
|
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
|
ti,mbox-rx = <2 0 2>;
|
|
ti,mbox-tx = <3 0 2>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster5 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster6 {
|
|
mbox_m4_0: mbox-m4-0 {
|
|
ti,mbox-rx = <0 0 2>;
|
|
ti,mbox-tx = <1 0 2>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster7 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&main_r5fss0_core0 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
|
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
|
<&main_r5fss0_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss0_core1 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
|
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
|
<&main_r5fss0_core1_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core0 {
|
|
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
|
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
|
<&main_r5fss1_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core1 {
|
|
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
|
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
|
<&main_r5fss1_core1_memory_region>;
|
|
};
|
|
|
|
&ecap0 {
|
|
status = "okay";
|
|
/* PWM is available on Pin 1 of header J3 */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_ecap0_pins_default>;
|
|
};
|