mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
arm: dts: k3-am64: sync with Linux DT files
Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Roger Quadros
Tom Rini
parent
9b26a251cf
commit
ffefc72083
6 changed files with 780 additions and 129 deletions
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@ -59,7 +59,10 @@
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01840000 0x00 0xC0000>; /* GICR */
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<0x00 0x01840000 0x00 0xC0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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@ -171,7 +174,7 @@
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 12>,
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mboxes = <&secure_proxy_main 12>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44043000 0x00 0xfe0>;
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@ -217,6 +220,12 @@
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reg = <0x4044 0x8>;
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#phy-cells = <1>;
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};
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epwm_tbclk: clock@4140 {
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compatible = "ti,am64-epwm-tbclk", "syscon";
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reg = <0x4130 0x4>;
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#clock-cells = <1>;
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};
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};
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main_uart0: serial@2800000 {
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@ -228,6 +237,7 @@
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart1: serial@2810000 {
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@ -239,6 +249,7 @@
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 152 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart2: serial@2820000 {
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@ -250,6 +261,7 @@
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 153 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart3: serial@2830000 {
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@ -261,6 +273,7 @@
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 154 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart4: serial@2840000 {
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@ -272,6 +285,7 @@
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power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 155 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart5: serial@2850000 {
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@ -283,6 +297,7 @@
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power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 156 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart6: serial@2860000 {
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@ -294,6 +309,7 @@
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power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 158 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_i2c0: i2c@20000000 {
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@ -305,6 +321,7 @@
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 102 2>;
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clock-names = "fck";
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status = "disabled";
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};
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main_i2c1: i2c@20010000 {
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@ -316,6 +333,7 @@
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power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 103 2>;
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clock-names = "fck";
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status = "disabled";
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};
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main_i2c2: i2c@20020000 {
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@ -327,6 +345,7 @@
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power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 104 2>;
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clock-names = "fck";
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status = "disabled";
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};
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main_i2c3: i2c@20030000 {
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@ -338,6 +357,7 @@
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power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 105 2>;
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clock-names = "fck";
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status = "disabled";
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};
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main_spi0: spi@20100000 {
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@ -350,6 +370,7 @@
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clocks = <&k3_clks 141 0>;
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dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
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dma-names = "tx0", "rx0";
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status = "disabled";
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};
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main_spi1: spi@20110000 {
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@ -360,6 +381,7 @@
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#size-cells = <0>;
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power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 142 0>;
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status = "disabled";
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};
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main_spi2: spi@20120000 {
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@ -370,6 +392,7 @@
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#size-cells = <0>;
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power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 143 0>;
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status = "disabled";
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};
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main_spi3: spi@20130000 {
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@ -380,6 +403,7 @@
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#size-cells = <0>;
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power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 144 0>;
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status = "disabled";
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};
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main_spi4: spi@20140000 {
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@ -390,6 +414,7 @@
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#size-cells = <0>;
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power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 145 0>;
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status = "disabled";
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};
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main_gpio_intr: interrupt-controller@a00000 {
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@ -447,13 +472,11 @@
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clock-names = "clk_ahb", "clk_xin";
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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ti,trm-icp = <0x2>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x6>;
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ti,otap-del-sel-hs200 = <0x7>;
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ti,otap-del-sel-hs400 = <0x4>;
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};
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sdhci1: mmc@fa00000 {
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@ -529,6 +552,7 @@
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clocks = <&k3_clks 13 0>;
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clock-names = "fck";
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bus_freq = <1000000>;
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status = "disabled";
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};
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cpts@3d000 {
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@ -543,7 +567,7 @@
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};
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};
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cpts@39000000 {
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main_cpts0: cpts@39000000 {
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compatible = "ti,j721e-cpts";
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reg = <0x0 0x39000000 0x0 0x400>;
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reg-names = "cpts";
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@ -558,6 +582,14 @@
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ti,cpts-ext-ts-inputs = <8>;
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};
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timesync_router: pinctrl@a40000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xa40000 0x0 0x800>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x000107ff>;
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};
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usbss0: cdns-usb@f900000{
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compatible = "ti,am64-usb";
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reg = <0x00 0xf900000 0x00 0x100>;
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@ -597,7 +629,7 @@
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assigned-clocks = <&k3_clks 0 0>;
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assigned-clock-parents = <&k3_clks 0 3>;
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assigned-clock-rates = <60000000>;
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clock-names = "adc_tsc_fck";
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clock-names = "fck";
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adc {
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#io-channel-cells = <1>;
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@ -840,6 +872,7 @@
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ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
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<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
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dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
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status = "disabled";
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};
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pcie0_ep: pcie-ep@f102000 {
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@ -858,23 +891,505 @@
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clocks = <&k3_clks 114 0>;
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clock-names = "fck";
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max-functions = /bits/ 8 <1>;
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status = "disabled";
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};
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epwm0: pwm@23000000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23000000 0x0 0x100>;
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power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm1: pwm@23010000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23010000 0x0 0x100>;
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power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm2: pwm@23020000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23020000 0x0 0x100>;
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power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm3: pwm@23030000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23030000 0x0 0x100>;
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power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm4: pwm@23040000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23040000 0x0 0x100>;
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power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm5: pwm@23050000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23050000 0x0 0x100>;
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power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm6: pwm@23060000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23060000 0x0 0x100>;
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power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm7: pwm@23070000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23070000 0x0 0x100>;
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power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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epwm8: pwm@23080000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x23080000 0x0 0x100>;
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power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
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clock-names = "tbclk", "fck";
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status = "disabled";
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};
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ecap0: pwm@23100000 {
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compatible = "ti,am64-ecap", "ti,am3352-ecap";
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#pwm-cells = <3>;
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reg = <0x0 0x23100000 0x0 0x60>;
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power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 51 0>;
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clock-names = "fck";
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status = "disabled";
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};
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ecap1: pwm@23110000 {
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compatible = "ti,am64-ecap", "ti,am3352-ecap";
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#pwm-cells = <3>;
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reg = <0x0 0x23110000 0x0 0x60>;
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power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 52 0>;
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clock-names = "fck";
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status = "disabled";
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};
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ecap2: pwm@23120000 {
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compatible = "ti,am64-ecap", "ti,am3352-ecap";
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#pwm-cells = <3>;
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reg = <0x0 0x23120000 0x0 0x60>;
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power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 53 0>;
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clock-names = "fck";
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status = "disabled";
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};
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main_rti0: watchdog@e000000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x00 0xe000000 0x00 0x100>;
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clocks = <&k3_clks 125 0>;
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power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 125 0>;
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assigned-clock-parents = <&k3_clks 125 2>;
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compatible = "ti,j7-rti-wdt";
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reg = <0x00 0xe000000 0x00 0x100>;
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clocks = <&k3_clks 125 0>;
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power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 125 0>;
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assigned-clock-parents = <&k3_clks 125 2>;
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};
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main_rti1: watchdog@e010000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x00 0xe010000 0x00 0x100>;
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clocks = <&k3_clks 126 0>;
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power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 126 0>;
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assigned-clock-parents = <&k3_clks 126 2>;
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compatible = "ti,j7-rti-wdt";
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reg = <0x00 0xe010000 0x00 0x100>;
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clocks = <&k3_clks 126 0>;
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power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 126 0>;
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assigned-clock-parents = <&k3_clks 126 2>;
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};
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icssg0: icssg@30000000 {
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compatible = "ti,am642-icssg";
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reg = <0x00 0x30000000 0x00 0x80000>;
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power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x30000000 0x80000>;
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icssg0_mem: memories@0 {
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reg = <0x0 0x2000>,
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<0x2000 0x2000>,
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<0x10000 0x10000>;
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reg-names = "dram0", "dram1", "shrdram2";
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};
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icssg0_cfg: cfg@26000 {
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compatible = "ti,pruss-cfg", "syscon";
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reg = <0x26000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x26000 0x2000>;
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clocks {
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#address-cells = <1>;
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||||
#size-cells = <0>;
|
||||
|
||||
icssg0_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
|
||||
<&k3_clks 81 20>; /* icssg0_iclk */
|
||||
assigned-clocks = <&icssg0_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 81 20>;
|
||||
};
|
||||
|
||||
icssg0_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */
|
||||
<&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */
|
||||
assigned-clocks = <&icssg0_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg0_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg0_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg0_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru0_0: pru@34000 {
|
||||
compatible = "ti,am642-pru";
|
||||
reg = <0x34000 0x3000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru0_0-fw";
|
||||
};
|
||||
|
||||
rtu0_0: rtu@4000 {
|
||||
compatible = "ti,am642-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu0_0-fw";
|
||||
};
|
||||
|
||||
tx_pru0_0: txpru@a000 {
|
||||
compatible = "ti,am642-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-txpru0_0-fw";
|
||||
};
|
||||
|
||||
pru0_1: pru@38000 {
|
||||
compatible = "ti,am642-pru";
|
||||
reg = <0x38000 0x3000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru0_1-fw";
|
||||
};
|
||||
|
||||
rtu0_1: rtu@6000 {
|
||||
compatible = "ti,am642-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu0_1-fw";
|
||||
};
|
||||
|
||||
tx_pru0_1: txpru@c000 {
|
||||
compatible = "ti,am642-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-txpru0_1-fw";
|
||||
};
|
||||
|
||||
icssg0_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 62 3>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
icssg1: icssg@30080000 {
|
||||
compatible = "ti,am642-icssg";
|
||||
reg = <0x00 0x30080000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x30080000 0x80000>;
|
||||
|
||||
icssg1_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1", "shrdram2";
|
||||
};
|
||||
|
||||
icssg1_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg1_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
|
||||
<&k3_clks 82 20>; /* icssg1_iclk */
|
||||
assigned-clocks = <&icssg1_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 82 20>;
|
||||
};
|
||||
|
||||
icssg1_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */
|
||||
<&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */
|
||||
assigned-clocks = <&icssg1_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg1_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg1_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg1_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru1_0: pru@34000 {
|
||||
compatible = "ti,am642-pru";
|
||||
reg = <0x34000 0x4000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru1_0-fw";
|
||||
};
|
||||
|
||||
rtu1_0: rtu@4000 {
|
||||
compatible = "ti,am642-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu1_0-fw";
|
||||
};
|
||||
|
||||
tx_pru1_0: txpru@a000 {
|
||||
compatible = "ti,am642-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-txpru1_0-fw";
|
||||
};
|
||||
|
||||
pru1_1: pru@38000 {
|
||||
compatible = "ti,am642-pru";
|
||||
reg = <0x38000 0x4000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru1_1-fw";
|
||||
};
|
||||
|
||||
rtu1_1: rtu@6000 {
|
||||
compatible = "ti,am642-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu1_1-fw";
|
||||
};
|
||||
|
||||
tx_pru1_1: txpru@c000 {
|
||||
compatible = "ti,am642-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-txpru1_1-fw";
|
||||
};
|
||||
|
||||
icssg1_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 82 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
main_mcan0: can@20701000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20701000 0x00 0x200>,
|
||||
<0x00 0x20708000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_mcan1: can@20711000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20711000 0x00 0x200>,
|
||||
<0x00 0x20718000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto: crypto@40900000 {
|
||||
compatible = "ti,am64-sa2ul";
|
||||
reg = <0x00 0x40900000 0x00 0x1200>;
|
||||
power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
|
||||
dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
|
||||
<&main_pktdma 0x4003 0>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
|
||||
rng: rng@40910000 {
|
||||
compatible = "inside-secure,safexcel-eip76";
|
||||
reg = <0x00 0x40910000 0x00 0x7d>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled"; /* Used by OP-TEE */
|
||||
};
|
||||
};
|
||||
|
||||
gpmc0: memory-controller@3b000000 {
|
||||
compatible = "ti,am64-gpmc";
|
||||
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 80 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x00 0x3b000000 0x00 0x400>,
|
||||
<0x00 0x50000000 0x00 0x8000000>;
|
||||
reg-names = "cfg", "data";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <3>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
elm0: ecc@25010000 {
|
||||
compatible = "ti,am64-elm";
|
||||
reg = <0x00 0x25010000 0x00 0x2000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 54 0>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,22 +10,22 @@
|
|||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_uart1: serial@4a10000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a10000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 160 0>;
|
||||
clock-names = "fclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@4900000 {
|
||||
|
|
@ -37,6 +37,7 @@
|
|||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@4910000 {
|
||||
|
|
@ -48,6 +49,7 @@
|
|||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 2>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@4b00000 {
|
||||
|
|
@ -58,6 +60,7 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 147 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_spi1: spi@4b10000 {
|
||||
|
|
@ -68,6 +71,7 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_gpio_intr: interrupt-controller@4210000 {
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@
|
|||
serial8 = &main_uart6;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
|
@ -80,6 +82,7 @@
|
|||
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
|
||||
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
|
||||
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
|
||||
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
|
||||
|
|
@ -88,6 +91,7 @@
|
|||
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-evm", "ti,am642";
|
||||
compatible = "ti,am642-evm", "ti,am642";
|
||||
model = "Texas Instruments AM642 EVM";
|
||||
|
||||
chosen {
|
||||
|
|
@ -184,6 +184,20 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
transceiver1: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
transceiver2: can-phy1 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -288,9 +302,30 @@
|
|||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_ecap0_pins_default: main-ecap0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan0_pins_default: main-mcan0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
|
||||
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan1_pins_default: main-mcan1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
|
||||
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
|
@ -300,35 +335,8 @@
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -371,23 +379,8 @@
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
|
|
@ -432,8 +425,7 @@
|
|||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
pinctrl-0 = <&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
|
|
@ -448,6 +440,10 @@
|
|||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default>;
|
||||
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
|
|
@ -464,7 +460,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
|
|
@ -475,8 +471,6 @@
|
|||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -562,6 +556,7 @@
|
|||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
|
|
@ -572,5 +567,25 @@
|
|||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
/* PWM is available on Pin 1 of header J12 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_ecap0_pins_default>;
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_pins_default>;
|
||||
phys = <&transceiver1>;
|
||||
};
|
||||
|
||||
&main_mcan1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan1_pins_default>;
|
||||
phys = <&transceiver2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,10 +9,11 @@
|
|||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-sk", "ti,am642";
|
||||
compatible = "ti,am642-sk", "ti,am642";
|
||||
model = "Texas Instruments AM642 SK";
|
||||
|
||||
chosen {
|
||||
|
|
@ -125,6 +126,99 @@
|
|||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
com8_ls_en: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "com8_ls_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
pinctrl-0 = <&main_com8_ls_en_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan_en: regulator-2 {
|
||||
/* output of SN74AVC4T245RSVR */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wlan_en";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
enable-active-high;
|
||||
pinctrl-0 = <&main_wlan_en_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
vin-supply = <&com8_ls_en>;
|
||||
gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-controller {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <1>;
|
||||
gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-1 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <2>;
|
||||
gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <3>;
|
||||
gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <4>;
|
||||
gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <5>;
|
||||
gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-5 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <6>;
|
||||
gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-6 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <7>;
|
||||
gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-7 {
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
function-enumerator = <8>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -141,6 +235,15 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb0_pins_default: main-usb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
|
|
@ -210,14 +313,35 @@
|
|||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_ecap0_pins_default: main-ecap0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
main_wlan_en_pins_default: main-wlan-en-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_wlan_pins_default: main-wlan-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
status = "disabled";
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
|
|
@ -225,35 +349,8 @@
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -268,18 +365,14 @@
|
|||
"VPP_LDO_EN", "RPI_PS_3V3_En",
|
||||
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi1 {
|
||||
status = "disabled";
|
||||
exp2: gpio@60 {
|
||||
compatible = "ti,tpic2810";
|
||||
reg = <0x60>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
|
||||
};
|
||||
};
|
||||
|
||||
/* mcu_gpio0 is reserved for mcu firmware usage */
|
||||
|
|
@ -287,6 +380,26 @@
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
vmmc-supply = <&wlan_en>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1837";
|
||||
reg = <2>;
|
||||
pinctrl-0 = <&main_wlan_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
|
|
@ -326,8 +439,7 @@
|
|||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
pinctrl-0 = <&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
|
|
@ -342,6 +454,10 @@
|
|||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default>;
|
||||
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
|
|
@ -363,7 +479,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
|
|
@ -374,8 +490,6 @@
|
|||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -446,10 +560,9 @@
|
|||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
status = "disabled";
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
/* PWM is available on Pin 1 of header J3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_ecap0_pins_default>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -60,6 +60,6 @@
|
|||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-sets = <256>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue