mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
111 lines
3.4 KiB
ArmAsm
111 lines
3.4 KiB
ArmAsm
/*
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* (C) Copyright 2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <ppc_asm.tmpl>
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#include <asm/mmu.h>
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#include <config.h>
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/*
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/* vxWorks needs this as first entry for the Machine Check interrupt */
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tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
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/*
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* The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
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* entry is already configured for SDRAM via the JTAG debugger and mustn't
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* be re-initialized by this RAM-booting U-Boot version.
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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/* TLB-entry for DDR SDRAM (Up to 2GB) */
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#ifdef CONFIG_4xx_DCACHE
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tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
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#else
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tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
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#endif
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#endif /* CONFIG_SYS_RAMBOOT */
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/* TLB-entry for EBC */
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tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
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/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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#ifndef CONFIG_NAND_SPL
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tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
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#else
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tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
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#endif
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#ifdef CONFIG_SYS_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
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#endif
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/* TLB-entry for PCI Memory */
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tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
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/* TLB-entry for NAND */
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tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
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/* TLB-entry for Internal Registers & OCM */
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tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
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/*TLB-entry PCI registers*/
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tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
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/* TLB-entry for peripherals */
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tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
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/* TLB-entry PCI IO Space - from sr@denx.de */
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tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
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tlbtab_end
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#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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/*
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* For NAND booting the first TLB has to be reconfigured to full size
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* and with caching disabled after running from RAM!
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*/
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#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
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#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
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#define TLB02 TLB2(AC_RWX | SA_IG)
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.globl reconfig_tlb0
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reconfig_tlb0:
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sync
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isync
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addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
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lis r5,TLB00@h
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ori r5,r5,TLB00@l
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tlbwe r5,r4,0x0000 /* Save it out */
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lis r5,TLB01@h
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ori r5,r5,TLB01@l
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tlbwe r5,r4,0x0001 /* Save it out */
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lis r5,TLB02@h
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ori r5,r5,TLB02@l
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tlbwe r5,r4,0x0002 /* Save it out */
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sync
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isync
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blr
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#endif
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