Murali Karicheri 6c343825dd ARM: keystone: ddr3: workaround for ddr3a/3b memory issue ... This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>		2014-09-17 21:06:56 -04:00
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clock-k2e.c	keystone2: use EFUSE_BOOTROM information to configure PLLs	2014-08-25 10:48:12 -04:00
clock-k2hk.c	keystone2: use EFUSE_BOOTROM information to configure PLLs	2014-08-25 10:48:12 -04:00
clock.c	ARM: keystone: clock: use correct BWADJ field mask for PASSPLLCTL0	2014-09-04 13:05:57 -04:00
cmd_clock.c	ARM: keystone2: clock: add K2E clock support	2014-07-25 16:26:11 -04:00
cmd_mon.c	k2hk: add support for k2hk SOC and EVM	2014-04-17 17:24:38 -04:00
ddr3.c	ARM: keystone: ddr3: workaround for ddr3a/3b memory issue	2014-09-17 21:06:56 -04:00
init.c	ARM: keystone2: add MSMC cache coherency support for K2E SOC	2014-07-25 16:26:11 -04:00
Kconfig	keystone: kconfig: move board select menu and common settings	2014-08-30 21:21:59 -04:00
keystone.c	k2hk: use common KS2_ prefix for all hardware definitions	2014-07-25 16:26:10 -04:00
keystone_nav.c	keystone2: add keystone multicore navigator driver	2014-04-17 17:24:39 -04:00
Makefile	ARM: keystone2: clock: add K2E clock support	2014-07-25 16:26:11 -04:00
msmc.c	ARM: keystone2: add MSMC cache coherency support for K2E SOC	2014-07-25 16:26:11 -04:00
psc.c	keystone2: use readl/writel functions instead of redefinition	2014-09-04 13:06:00 -04:00
spl.c	ARM: keystone2: spl: add K2E SoC support	2014-07-25 16:26:11 -04:00