u-boot/board/gdsys
York Sun 316f0d0f8f powerpc: mpc85xx: Fix static TLB table for SDRAM
Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-12-06 14:54:12 -08:00
..
a38x arm: mvebu: correct comments around cas_wl/cas_l 2017-11-30 08:30:59 +01:00
common strider: Support con-dp flavor 2016-06-06 13:39:13 -04:00
mpc8308 MAINTAINERS: Add missing boards and config entries 2017-11-06 09:58:51 -05:00
p1022 powerpc: mpc85xx: Fix static TLB table for SDRAM 2017-12-06 14:54:12 -08:00