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u-boot/arch/riscv/dts
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Niklas Cassel 530f29cba5 k210: dts: align plic node with Linux 
The Linux PLIC interrupt-controller driver actually initializes the hart
context registers in the PLIC driver exactly in the same order as
specified in the interrupts-extended device tree property. See the device
tree binding [1].

The ordering of the interrupts is therefore essential in order to
configure the PLIC correctly.

Fix the order so that we will have sane IRQ behavior when booting Linux
with the u-boot device tree.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15 17:43:11 +08:00
..
ae350-u-boot.dtsi riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config 2021-06-17 09:39:08 +08:00
ae350_32.dts riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config 2021-06-17 09:39:08 +08:00
ae350_64.dts riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config 2021-06-17 09:39:08 +08:00
binman.dtsi riscv: Remove OF_PRIOR_STAGE from RISC-V boards 2021-10-18 13:19:50 -04:00
fu540-c000-u-boot.dtsi riscv: fu540: dts: Correct reg size of clint node 2020-10-26 10:01:37 +08:00
fu540-c000.dtsi riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux 2020-06-04 09:44:09 +08:00
fu540-hifive-unleashed-a00-ddr.dtsi sifive: dts: fu540: Add DDR controller and phy register settings 2020-06-04 09:44:08 +08:00
fu740-c000-u-boot.dtsi riscv: sifive: fu740: Support i2c in spl 2021-07-06 20:24:25 +08:00
fu740-c000.dtsi riscv: dts: add fu740 support 2021-05-31 16:35:54 +08:00
fu740-hifive-unmatched-a00-ddr.dtsi riscv: dts: add SiFive Unmatched board support 2021-05-31 16:35:54 +08:00
hifive-unleashed-a00-u-boot.dtsi riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb 2021-05-19 17:01:50 +08:00
hifive-unleashed-a00.dts riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux 2020-06-04 09:44:09 +08:00
hifive-unmatched-a00-u-boot.dtsi riscv: Support booting SiFive Unmatched from SPI. 2021-12-02 16:43:56 +08:00
hifive-unmatched-a00.dts riscv: dts: add SiFive Unmatched board support 2021-05-31 16:35:54 +08:00
k210-maix-bit.dts k210: use the board vendor name rather than the marketing name 2022-03-15 17:43:11 +08:00
k210.dtsi k210: dts: align plic node with Linux 2022-03-15 17:43:11 +08:00
Makefile dts: automatically build necessary .dtb files 2022-02-09 12:26:12 -07:00
microchip-mpfs-icicle-kit-u-boot.dtsi riscv: dts: Add device tree for Microchip Icicle Kit 2021-01-18 11:06:38 +08:00
microchip-mpfs-icicle-kit.dts riscv: dts: Split Microchip device tree 2021-12-02 16:43:51 +08:00
microchip-mpfs.dtsi riscv: dts: Split Microchip device tree 2021-12-02 16:43:51 +08:00
openpiton-riscv64.dts riscv: dts: add OpenPiton RISC-V board dts support 2021-07-07 20:34:02 +08:00
qemu-virt32.dts riscv: qemu: Split devicetree files for qemu_riscv32/64 2021-12-23 10:24:39 -05:00
qemu-virt64.dts riscv: qemu: Split devicetree files for qemu_riscv32/64 2021-12-23 10:24:39 -05:00