Daniel Schwierzeck 65d297af7c MIPS: fix iand optimize setup of CP0 registers ... Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>		2016-11-30 16:11:46 +01:00
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mips32	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
mips64	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
cm_init.S	MIPS: Map CM Global Control Registers	2016-09-21 15:04:04 +02:00
cpu.c	MIPS: Probe cache line sizes once during boot	2016-09-21 15:04:04 +02:00
interrupts.c	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
Makefile	MIPS: Map CM Global Control Registers	2016-09-21 15:04:04 +02:00
start.S	MIPS: fix iand optimize setup of CP0 registers	2016-11-30 16:11:46 +01:00
time.c	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
u-boot-spl.lds	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
u-boot.lds	MIPS: Fix cache maintenance in relocate_code & simplify	2016-09-21 16:25:43 +02:00