mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 03:23:47 +00:00
35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
398 lines
9.1 KiB
C
398 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* board/renesas/lager/lager_spl.c
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <malloc.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <spl.h>
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#define TMU0_MSTP125 BIT(25)
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#define SCIF0_MSTP721 BIT(21)
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#define QSPI_MSTP917 BIT(17)
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#define SD2CKCR 0xE615026C
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#define SD_97500KHZ 0x7
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struct reg_config {
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u16 off;
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u32 val;
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};
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static void dbsc_wait(u16 reg)
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{
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static const u32 dbsc3_0_base = DBSC3_0_BASE;
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while (!(readl(dbsc3_0_base + reg) & BIT(0)))
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;
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}
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static void spl_init_sys(void)
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{
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u32 r0 = 0;
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writel(0xa5a5a500, 0xe6020004);
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writel(0xa5a5a500, 0xe6030004);
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asm volatile(
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/* ICIALLU - Invalidate I$ to PoU */
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"mcr 15, 0, %0, cr7, cr5, 0 \n"
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/* BPIALL - Invalidate branch predictors */
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"mcr 15, 0, %0, cr7, cr5, 6 \n"
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/* Set SCTLR[IZ] */
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"mrc 15, 0, %0, cr1, cr0, 0 \n"
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"orr %0, #0x1800 \n"
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"mcr 15, 0, %0, cr1, cr0, 0 \n"
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"isb sy \n"
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:"=r"(r0));
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}
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static void spl_init_pfc(void)
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{
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static const struct reg_config pfc_with_unlock[] = {
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{ 0x0090, 0x00000000 },
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{ 0x0094, 0x00000000 },
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{ 0x0098, 0xc0000000 },
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{ 0x0020, 0x00000000 },
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{ 0x0024, 0x00000000 },
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{ 0x0028, 0x00000000 },
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{ 0x002c, 0x20000000 },
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{ 0x0030, 0x00001249 },
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{ 0x0034, 0x00000278 },
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{ 0x0038, 0x00000841 },
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{ 0x003c, 0x00000000 },
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{ 0x0040, 0x00000000 },
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{ 0x0044, 0x10000000 },
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{ 0x0048, 0x00000001 },
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{ 0x004c, 0x0004aab0 },
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{ 0x0050, 0x37301b00 },
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{ 0x0054, 0x00048da3 },
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{ 0x0058, 0x089044a1 },
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{ 0x005c, 0x2a3a55b4 },
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{ 0x0160, 0x00000003 },
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{ 0x0004, 0xffffffff },
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{ 0x0008, 0x2aef3fff },
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{ 0x000c, 0x3fffffff },
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{ 0x0010, 0xff7fc07f },
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{ 0x0014, 0x7f3ff3f8 },
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{ 0x0018, 0x1cfdfff7 },
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};
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static const struct reg_config pfc_without_unlock[] = {
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{ 0x0100, 0x1fffffff },
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{ 0x0104, 0xffff0318 },
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{ 0x0108, 0x387fffe1 },
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{ 0x010c, 0x00803f80 },
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{ 0x0110, 0x1520009f },
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{ 0x0114, 0x00000000 },
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{ 0x0118, 0x00000000 },
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};
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static const u32 pfc_base = 0xe6060000;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
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writel(~pfc_with_unlock[i].val, pfc_base);
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writel(pfc_with_unlock[i].val,
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pfc_base | pfc_with_unlock[i].off);
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}
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for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
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writel(pfc_without_unlock[i].val,
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pfc_base | pfc_without_unlock[i].off);
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}
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static void spl_init_gpio(void)
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{
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static const u16 gpio_offs[] = {
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0x1000, 0x3000, 0x4000, 0x5000
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};
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static const struct reg_config gpio_set[] = {
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{ 0x4000, 0x00c00000 },
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{ 0x5000, 0x63020000 },
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};
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static const struct reg_config gpio_clr[] = {
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{ 0x1000, 0x00000000 },
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{ 0x3000, 0x00000000 },
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{ 0x4000, 0x00c00000 },
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{ 0x5000, 0xe3020000 },
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};
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static const u32 gpio_base = 0xe6050000;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
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writel(0, gpio_base | 0x20 | gpio_offs[i]);
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
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writel(0, gpio_base | 0x00 | gpio_offs[i]);
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for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
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writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
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for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
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writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
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}
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static void spl_init_lbsc(void)
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{
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static const struct reg_config lbsc_config[] = {
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{ 0x00, 0x00000020 },
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{ 0x08, 0x00002020 },
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{ 0x30, 0x02150326 },
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{ 0x38, 0x077f077f },
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};
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static const u16 lbsc_offs[] = {
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0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
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};
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static const u32 lbsc_base = 0xfec00200;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
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writel(lbsc_config[i].val,
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lbsc_base | lbsc_config[i].off);
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writel(lbsc_config[i].val,
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lbsc_base | (lbsc_config[i].off + 4));
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}
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for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
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writel(0, lbsc_base | lbsc_offs[i]);
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}
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static void spl_init_dbsc(void)
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{
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static const struct reg_config dbsc_config1[] = {
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{ 0x0018, 0x21000000 },
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{ 0x0018, 0x11000000 },
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{ 0x0018, 0x10000000 },
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{ 0x0280, 0x0000a55a },
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x80000000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config4[] = {
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{ 0x0290, 0x00000010 },
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{ 0x02a0, 0xf004649b },
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{ 0x0290, 0x0000000f },
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{ 0x02a0, 0x00181ee4 },
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{ 0x0290, 0x00000060 },
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{ 0x02a0, 0x330657b2 },
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x00000071 },
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{ 0x0020, 0x00000007 },
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{ 0x0024, 0x10030a02 },
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{ 0x0030, 0x00000001 },
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{ 0x00b0, 0x00000000 },
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{ 0x0040, 0x0000000b },
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{ 0x0044, 0x00000008 },
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{ 0x0048, 0x00000000 },
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{ 0x0050, 0x0000000b },
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{ 0x0054, 0x000c000b },
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{ 0x0058, 0x00000027 },
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{ 0x005c, 0x0000001c },
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{ 0x0060, 0x00000005 },
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{ 0x0064, 0x00000018 },
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{ 0x0068, 0x00000008 },
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{ 0x006c, 0x0000000c },
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{ 0x0070, 0x00000009 },
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{ 0x0074, 0x00000012 },
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{ 0x0078, 0x000000d0 },
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{ 0x007c, 0x00140005 },
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{ 0x0080, 0x00050004 },
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{ 0x0084, 0x70233005 },
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{ 0x0088, 0x000c0000 },
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{ 0x008c, 0x00000300 },
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{ 0x0090, 0x00000040 },
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{ 0x0100, 0x00000001 },
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{ 0x00c0, 0x00020001 },
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{ 0x00c8, 0x20082008 },
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{ 0x0380, 0x00020002 },
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{ 0x0390, 0x0000000f },
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};
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static const struct reg_config dbsc_config5[] = {
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{ 0x0244, 0x00000011 },
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{ 0x0290, 0x00000006 },
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{ 0x02a0, 0x0005c000 },
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{ 0x0290, 0x00000003 },
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{ 0x02a0, 0x0300c481 },
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{ 0x0290, 0x00000023 },
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{ 0x02a0, 0x00fdb6c0 },
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{ 0x0290, 0x00000011 },
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{ 0x02a0, 0x1000040b },
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{ 0x0290, 0x00000012 },
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{ 0x02a0, 0x9d5cbb66 },
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{ 0x0290, 0x00000013 },
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{ 0x02a0, 0x1a868300 },
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{ 0x0290, 0x00000014 },
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{ 0x02a0, 0x300214d8 },
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{ 0x0290, 0x00000015 },
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{ 0x02a0, 0x00000d70 },
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{ 0x0290, 0x00000016 },
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{ 0x02a0, 0x00000006 },
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{ 0x0290, 0x00000017 },
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{ 0x02a0, 0x00000018 },
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{ 0x0290, 0x0000001a },
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{ 0x02a0, 0x910035c7 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config6[] = {
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x00000181 },
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{ 0x0018, 0x11000000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config7[] = {
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x0000fe01 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config8[] = {
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{ 0x0304, 0x00000000 },
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{ 0x00f4, 0x01004c20 },
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{ 0x00f8, 0x014000aa },
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{ 0x00e0, 0x00000140 },
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{ 0x00e4, 0x00081860 },
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{ 0x00e8, 0x00010000 },
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{ 0x0014, 0x00000001 },
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{ 0x0010, 0x00000001 },
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{ 0x0280, 0x00000000 },
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};
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static const u32 dbsc3_0_base = DBSC3_0_BASE;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
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writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
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writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
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dbsc_wait(0x240);
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for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
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writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
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writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
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writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
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writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
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}
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static void spl_init_qspi(void)
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{
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
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static const u32 qspi_base = 0xe6b10000;
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writeb(0x08, qspi_base + 0x00);
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writeb(0x00, qspi_base + 0x01);
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writeb(0x06, qspi_base + 0x02);
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writeb(0x01, qspi_base + 0x0a);
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writeb(0x00, qspi_base + 0x0b);
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writeb(0x00, qspi_base + 0x0c);
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writeb(0x00, qspi_base + 0x0d);
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writeb(0x00, qspi_base + 0x0e);
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writew(0xe080, qspi_base + 0x10);
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writeb(0xc0, qspi_base + 0x18);
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writeb(0x00, qspi_base + 0x18);
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writeb(0x00, qspi_base + 0x08);
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writeb(0x48, qspi_base + 0x00);
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}
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void board_init_f(ulong dummy)
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{
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD2 to the 97.5MHz as well.
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*/
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writel(SD_97500KHZ, SD2CKCR);
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spl_init_sys();
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spl_init_pfc();
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spl_init_gpio();
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spl_init_lbsc();
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spl_init_dbsc();
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spl_init_qspi();
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}
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void spl_board_init(void)
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{
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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const u32 jtag_magic = 0x1337c0de;
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const u32 load_magic = 0xb33fc0de;
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/*
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* If JTAG probe sets special word at 0xe6300020, then it must
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* put U-Boot into RAM and SPL will start it from RAM.
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*/
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if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
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printf("JTAG boot detected!\n");
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while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
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;
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spl_boot_list[0] = BOOT_DEVICE_RAM;
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spl_boot_list[1] = BOOT_DEVICE_NONE;
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return;
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}
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/* Boot from SPI NOR with YMODEM UART fallback. */
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spl_boot_list[0] = BOOT_DEVICE_SPI;
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spl_boot_list[1] = BOOT_DEVICE_UART;
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spl_boot_list[2] = BOOT_DEVICE_NONE;
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}
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void reset_cpu(void)
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{
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}
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