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https://github.com/AsahiLinux/u-boot
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1045ff4d1a
The commit 1b42ab3eda ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.
The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
312 lines
7.9 KiB
C
312 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Texas Instruments, Inc.
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*/
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#include <common.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <malloc.h>
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#include <asm/omap_common.h>
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#include <asm/arch-omap5/sys_proto.h>
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#ifdef CONFIG_TI_SECURE_DEVICE
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/* Give zero values if not already defined */
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#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
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#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
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#endif
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#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
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#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
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#endif
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static u32 hs_irq_skip[] = {
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8, /* Secure violation reporting interrupt */
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15, /* One interrupt for SDMA by secure world */
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118 /* One interrupt for Crypto DMA by secure world */
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};
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static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
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{
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const char *path;
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int offs;
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int ret;
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int len, i, old_cnt, new_cnt;
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u32 *temp;
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const u32 *p_data;
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/*
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* Increase the size of the fdt
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* so we have some breathing room
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*/
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ret = fdt_increase_size(fdt, 512);
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if (ret < 0) {
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printf("Could not increase size of device tree: %s\n",
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fdt_strerror(ret));
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return ret;
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}
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/* Reserve IRQs that are used/needed by secure world */
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path = "/ocp/crossbar";
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offs = fdt_path_offset(fdt, path);
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if (offs < 0) {
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debug("Node %s not found.\n", path);
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return 0;
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}
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/* Get current entries */
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p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
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if (p_data)
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old_cnt = len / sizeof(u32);
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else
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old_cnt = 0;
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new_cnt = sizeof(hs_irq_skip) /
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sizeof(hs_irq_skip[0]);
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/* Create new/updated skip list for HS parts */
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temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
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for (i = 0; i < new_cnt; i++)
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temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
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for (i = 0; i < old_cnt; i++)
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temp[i + new_cnt] = p_data[i];
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/* Blow away old data and set new data */
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fdt_delprop(fdt, offs, "ti,irqs-skip");
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ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
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temp,
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(old_cnt + new_cnt) * sizeof(u32));
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free(temp);
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/* Check if the update worked */
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if (ret < 0) {
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printf("Could not add ti,irqs-skip property to node %s: %s\n",
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path, fdt_strerror(ret));
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return ret;
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}
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return 0;
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}
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#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
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(CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
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static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
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{
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const char *path;
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int offs;
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int ret;
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u32 temp[2];
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/*
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* Update SRAM reservations on secure devices. The OCMC RAM
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* is always reserved for secure use from the start of that
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* memory region
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*/
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path = "/ocp/ocmcram@40300000/sram-hs";
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offs = fdt_path_offset(fdt, path);
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if (offs < 0) {
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debug("Node %s not found.\n", path);
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return 0;
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}
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/* relative start offset */
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temp[0] = cpu_to_fdt32(0);
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/* reservation size */
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temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
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CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
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fdt_delprop(fdt, offs, "reg");
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ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
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if (ret < 0) {
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printf("Could not add reg property to node %s: %s\n",
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path, fdt_strerror(ret));
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return ret;
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}
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return 0;
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}
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#else
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static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
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#endif
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static void ft_hs_fixups(void *fdt, bd_t *bd)
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{
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/* Check we are running on an HS/EMU device type */
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if (GP_DEVICE != get_device_type()) {
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if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
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(ft_hs_disable_rng(fdt, bd) == 0) &&
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(ft_hs_fixup_sram(fdt, bd) == 0) &&
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(ft_hs_fixup_dram(fdt, bd) == 0) &&
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(ft_hs_add_tee(fdt, bd) == 0))
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return;
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} else {
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printf("ERROR: Incorrect device type (GP) detected!");
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}
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/* Fixup failed or wrong device type */
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hang();
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}
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#else
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static void ft_hs_fixups(void *fdt, bd_t *bd)
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{
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}
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#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
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#if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
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#define OPP_DSP_CLK_NUM 3
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#define OPP_IVA_CLK_NUM 2
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#define OPP_GPU_CLK_NUM 2
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const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
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"dpll_dsp_ck",
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"dpll_dsp_m2_ck",
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"dpll_dsp_m3x2_ck",
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};
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const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
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"dpll_iva_ck",
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"dpll_iva_m2_ck",
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};
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const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
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"dpll_gpu_ck",
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"dpll_gpu_m2_ck",
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};
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/* DSPEVE voltage domain */
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u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
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{}, /*OPP_LOW */
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{600000000, 600000000, 400000000}, /* OPP_NOM */
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{700000000, 700000000, 466666667}, /* OPP_OD */
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{750000000, 750000000, 500000000}, /* OPP_HIGH */
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};
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/* DSP clock rates on DRA76x ACD-package based SoCs */
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u32 dra76_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
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{}, /* OPP_LOW */
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{600000000, 600000000, 400000000}, /* OPP_NOM */
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{700000000, 700000000, 466666667}, /* OPP_OD */
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{850000000, 850000000, 566666667}, /* OPP_HIGH */
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};
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/* IVA voltage domain */
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u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
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{}, /* OPP_LOW */
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{1165000000, 388333334}, /* OPP_NOM */
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{860000000, 430000000}, /* OPP_OD */
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{1064000000, 532000000}, /* OPP_HIGH */
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};
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/* GPU voltage domain */
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u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
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{}, /* OPP_LOW */
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{1277000000, 425666667}, /* OPP_NOM */
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{1000000000, 500000000}, /* OPP_OD */
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{1064000000, 532000000}, /* OPP_HIGH */
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};
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static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
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{
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int offs, node_offs, ret, i;
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uint32_t phandle;
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offs = fdt_path_offset(fdt, "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks");
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if (offs < 0)
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offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
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if (offs < 0) {
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debug("Could not find cm_core_aon clocks node path offset : %s\n",
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fdt_strerror(offs));
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return offs;
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}
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for (i = 0; i < num; i++) {
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node_offs = fdt_subnode_offset(fdt, offs, names[i]);
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if (node_offs < 0) {
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debug("Could not find clock sub-node %s: %s\n",
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names[i], fdt_strerror(node_offs));
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return offs;
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}
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phandle = fdt_get_phandle(fdt, node_offs);
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if (!phandle) {
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debug("Could not find phandle for clock %s\n",
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names[i]);
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return -1;
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}
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ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
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phandle);
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if (ret < 0) {
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debug("Could not add assigned-clocks property to clock node %s: %s\n",
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names[i], fdt_strerror(ret));
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return ret;
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}
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ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
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rates[i]);
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if (ret < 0) {
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debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
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names[i], fdt_strerror(ret));
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return ret;
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}
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}
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return 0;
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}
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static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
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{
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const char **clk_names;
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u32 *clk_rates;
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int ret;
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if (!is_dra72x() && !is_dra7xx())
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return;
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/* fixup DSP clocks */
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clk_names = dra7_opp_dsp_clk_names;
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clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
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/* adjust for higher OPP_HIGH clock rate on DRA76xP/DRA77xP SoCs */
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if (is_dra76x_acd())
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clk_rates = dra76_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
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ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
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if (ret) {
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printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
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fdt_strerror(ret));
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return;
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}
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/* fixup IVA clocks */
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clk_names = dra7_opp_iva_clk_names;
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clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
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ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
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if (ret) {
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printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
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fdt_strerror(ret));
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return;
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}
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/* fixup GPU clocks */
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clk_names = dra7_opp_gpu_clk_names;
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clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
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ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
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if (ret) {
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printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
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fdt_strerror(ret));
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return;
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}
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}
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#else
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static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { }
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#endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
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/*
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* Place for general cpu/SoC FDT fixups. Board specific
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* fixups should remain in the board files which is where
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* this function should be called from.
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*/
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void ft_cpu_setup(void *fdt, bd_t *bd)
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{
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ft_hs_fixups(fdt, bd);
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ft_opp_clock_fixups(fdt, bd);
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}
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