mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
b5fe523bbc
Sync the device tree files and device tree header files from upstream
Linux kernel, as of 2020-01-08. The commit synced to in the sunxi repo
98d25b0b266d Merge branch 'sunxi/dt-for-5.6' into sunxi/for-next
which is also part of next-20200108.
Changes brought in include:
- cleanup of pinmux node names
- addition of Security ID, MBUS, CSI, crypto engine, video codec,
pmu, and thermal sensor device nodes for both SoCs
- addition of deinterlacing engine device node on H3
- cleanup of RTC device node and addition of its clocks
- various board cleanups and improvements
- removal of pinmux node for GPIO lines
- cpufreq / DVFS
- HDMI output
- UART-based Bluetooth
- audio codec
- USB ports
- new boards
Most of the changes don't concern U-boot.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
288 lines
7.7 KiB
Text
288 lines
7.7 KiB
Text
/*
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "sunxi-h3-h5.dtsi"
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/ {
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-648000000 {
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opp-hz = /bits/ 64 <648000000>;
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opp-microvolt = <1040000 1040000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1100000 1100000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1200000 1200000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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deinterlace: deinterlace@1400000 {
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compatible = "allwinner,sun8i-h3-deinterlace";
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reg = <0x01400000 0x20000>;
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clocks = <&ccu CLK_BUS_DEINTERLACE>,
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<&ccu CLK_DEINTERLACE>,
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<&ccu CLK_DRAM_DEINTERLACE>;
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clock-names = "bus", "mod", "ram";
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resets = <&ccu RST_BUS_DEINTERLACE>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&mbus 9>;
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interconnect-names = "dma-mem";
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};
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syscon: system-control@1c00000 {
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compatible = "allwinner,sun8i-h3-system-control";
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reg = <0x01c00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_c: sram@1d00000 {
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compatible = "mmio-sram";
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reg = <0x01d00000 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x01d00000 0x80000>;
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ve_sram: sram-section@0 {
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compatible = "allwinner,sun8i-h3-sram-c1",
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"allwinner,sun4i-a10-sram-c1";
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reg = <0x000000 0x80000>;
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun8i-h3-video-engine";
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reg = <0x01c0e000 0x1000>;
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clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_VE>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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allwinner,sram = <&ve_sram 1>;
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};
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crypto: crypto@1c15000 {
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compatible = "allwinner,sun8i-h3-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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clock-names = "bus", "mod";
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resets = <&ccu RST_BUS_CE>;
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};
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mali: gpu@1c40000 {
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compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
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reg = <0x01c40000 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pmu";
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clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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clock-names = "bus", "core";
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resets = <&ccu RST_BUS_GPU>;
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assigned-clocks = <&ccu CLK_GPU>;
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assigned-clock-rates = <384000000>;
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};
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ths: thermal-sensor@1c25000 {
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compatible = "allwinner,sun8i-h3-ths";
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reg = <0x01c25000 0x400>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_BUS_THS>;
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clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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clock-names = "bus", "mod";
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nvmem-cells = <&ths_calibration>;
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nvmem-cell-names = "calibration";
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#thermal-sensor-cells = <0>;
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};
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 0>;
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};
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};
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};
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&ccu {
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compatible = "allwinner,sun8i-h3-ccu";
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};
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&display_clocks {
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compatible = "allwinner,sun8i-h3-de2-clk";
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};
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&mmc0 {
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compatible = "allwinner,sun7i-a20-mmc";
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clocks = <&ccu CLK_BUS_MMC0>,
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<&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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};
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&mmc1 {
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compatible = "allwinner,sun7i-a20-mmc";
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clocks = <&ccu CLK_BUS_MMC1>,
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<&ccu CLK_MMC1>,
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<&ccu CLK_MMC1_OUTPUT>,
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<&ccu CLK_MMC1_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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};
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&mmc2 {
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compatible = "allwinner,sun7i-a20-mmc";
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clocks = <&ccu CLK_BUS_MMC2>,
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<&ccu CLK_MMC2>,
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<&ccu CLK_MMC2_OUTPUT>,
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<&ccu CLK_MMC2_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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};
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&pio {
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compatible = "allwinner,sun8i-h3-pinctrl";
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};
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&rtc {
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compatible = "allwinner,sun8i-h3-rtc";
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};
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&sid {
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compatible = "allwinner,sun8i-h3-sid";
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};
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