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54351fe542
Add support to Verdin IMX8MP V1.1B SKU which uses MT53E1G32D2FW-046 WT:B memory. Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on Verdin IMX8MP V1.0A it has 16 row addresses instead of 17. In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a 4 GB/rank memory. Manually tweaking Host Interface addresses vs LPDDR4 signals mapping it is possible to have a single configuration working with both memories: - Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16 - New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16 With this change the memory space from the host processor is contiguous for both the configurations and the correct memory size is computed using get_ram_size() at runtime. Support for single rank memories still works thanks to the fact dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank memories. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> |
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| .. | ||
| imximage.cfg | ||
| Kconfig | ||
| lpddr4_timing.c | ||
| MAINTAINERS | ||
| Makefile | ||
| spl.c | ||
| verdin-imx8mp.c | ||