u-boot/arch/arm/cpu/armv7/omap5
Nishanth Menon 67055bee25 ARM: DRA7: Change configuration to prevent DDR reset control from EMIF
DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.

The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".

Fixes: 536d874708 ("ARM: DRA7: Update DDR IO registers")
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-19 16:46:48 -04:00
..
abb.c DRA7: add ABB setup for MPU voltage domain 2014-01-24 11:41:17 -05:00
config.mk kbuild: use shorten logs for mkimage rules 2014-02-25 11:01:29 -05:00
dra7xx_iodelay.c ARM: DRA7: Add support for manual mode configuration 2015-06-12 13:02:05 -04:00
emif.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
hw_data.c ARM: DRA7: Change configuration to prevent DDR reset control from EMIF 2015-06-19 16:46:48 -04:00
hwinit.c am33xx: Re-enable SW levelling for DDR2 2015-06-15 10:57:26 -04:00
Kconfig arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
Makefile ARM: DRA7: Add support for IO delay configuration 2015-06-12 13:02:05 -04:00
prcm-regs.c ARM: BeagleBoard-x15: Enable i2c5 clocks 2015-06-15 10:57:26 -04:00
sdram.c ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register 2015-06-12 12:43:07 -04:00