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ef6fcab85f
Current pin control driver applies SDHCI PHY MUX selection when board DT calls for eMMC function on MPP wires. However, for CP side eMMC, only the "armada-8k-cpm-pinctrl" compatibility string is taken into account, which causes CP-SDHCI on Armada-7K boards to fail. This patch adds "armada-7k-pinctrl" compatibility string handling for the CP-SDHCI PHY configuration case. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
238 lines
6.5 KiB
C
238 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 Marvell International Ltd.
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* https://spdx.org/licenses
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*/
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#include <common.h>
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#include <config.h>
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#include <fdtdec.h>
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#include <errno.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/arch-armada8k/soc-info.h>
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#include <linux/bitops.h>
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#include "pinctrl-mvebu.h"
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#define AP_EMMC_PHY_CTRL_REG 0x100
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#define CP_EMMC_PHY_CTRL_REG 0x424
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#define EMMC_PHY_CTRL_SDPHY_EN BIT(0)
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#define AP806_EMMC_CLK_PIN_ID 0
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#define AP806_EMMC_CLK_FUNC 0x1
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#define CP110_EMMC_CLK_PIN_ID 56
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#define CP110_EMMC_CLK_FUNC 0xe
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DECLARE_GLOBAL_DATA_PTR;
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/* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux
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* To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux.
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* eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC
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* controller:
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* - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer,
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* - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller
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* If pin function is set to eMMC/SD, then configure the eMMC/SD PHY
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* muxltiplexer register to be on SDIO/eMMC controller
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*/
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void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func)
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{
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(dev);
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struct mvebu_pinctrl_priv *priv = dev_get_priv(dev);
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if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) {
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if ((pin == AP806_EMMC_CLK_PIN_ID) &&
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(func == AP806_EMMC_CLK_FUNC)) {
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clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,
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EMMC_PHY_CTRL_SDPHY_EN);
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}
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} else if (!fdt_node_check_compatible(blob, node,
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"marvell,armada-8k-cpm-pinctrl") ||
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!fdt_node_check_compatible(blob, node,
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"marvell,armada-7k-pinctrl")) {
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if ((pin == CP110_EMMC_CLK_PIN_ID) &&
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(func == CP110_EMMC_CLK_FUNC)) {
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clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,
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EMMC_PHY_CTRL_SDPHY_EN);
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}
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}
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}
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/*
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* mvebu_pinctrl_set_state: configure pin functions.
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* @dev: the pinctrl device to be configured.
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* @config: the state to be configured.
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* @return: 0 in success
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*/
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int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(config);
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struct mvebu_pinctrl_priv *priv;
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u32 pin_arr[MVEBU_MAX_PINS_PER_BANK];
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u32 function;
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int i, pin_count;
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priv = dev_get_priv(dev);
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pin_count = fdtdec_get_int_array_count(blob, node,
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"marvell,pins",
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pin_arr,
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MVEBU_MAX_PINS_PER_BANK);
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if (pin_count <= 0) {
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debug("Failed reading pins array for pinconfig %s (%d)\n",
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config->name, pin_count);
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return -EINVAL;
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}
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function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
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/*
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* Check if setup of PHY mux is needed for this pins group.
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* Only the first pin id in array is tested, all the rest use the same
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* pin function.
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*/
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mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function);
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for (i = 0; i < pin_count; i++) {
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int reg_offset;
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int field_offset;
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int pin = pin_arr[i];
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if (function > priv->max_func) {
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debug("Illegal function %d for pinconfig %s\n",
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function, config->name);
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return -EINVAL;
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}
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/* Calculate register address and bit in register */
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reg_offset = priv->reg_direction * 4 *
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(pin >> (PIN_REG_SHIFT));
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field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
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clrsetbits_le32(priv->base_reg + reg_offset,
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PIN_FUNC_MASK << field_offset,
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(function & PIN_FUNC_MASK) << field_offset);
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}
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return 0;
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}
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/*
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* mvebu_pinctrl_set_state_all: configure the entire bank pin functions.
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* @dev: the pinctrl device to be configured.
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* @config: the state to be configured.
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* @return: 0 in success
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*/
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static int mvebu_pinctrl_set_state_all(struct udevice *dev,
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struct udevice *config)
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{
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(config);
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struct mvebu_pinctrl_priv *priv;
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u32 func_arr[MVEBU_MAX_PINS_PER_BANK];
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int pin, err;
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priv = dev_get_priv(dev);
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err = fdtdec_get_int_array(blob, node, "pin-func",
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func_arr, priv->pin_cnt);
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if (err) {
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debug("Failed reading pin functions for bank %s\n",
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priv->bank_name);
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return -EINVAL;
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}
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/* Check if setup of PHY mux is needed for this pins group. */
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if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID)
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mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID,
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func_arr[AP806_EMMC_CLK_PIN_ID]);
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else
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mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID,
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func_arr[CP110_EMMC_CLK_PIN_ID]);
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for (pin = 0; pin < priv->pin_cnt; pin++) {
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int reg_offset;
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int field_offset;
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u32 func = func_arr[pin];
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/* Bypass pins with function 0xFF */
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if (func == 0xff) {
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debug("Warning: pin %d value is not modified ", pin);
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debug("(kept as default)\n");
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continue;
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} else if (func > priv->max_func) {
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debug("Illegal function %d for pin %d\n", func, pin);
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return -EINVAL;
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}
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/* Calculate register address and bit in register */
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reg_offset = priv->reg_direction * 4 *
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(pin >> (PIN_REG_SHIFT));
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field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
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clrsetbits_le32(priv->base_reg + reg_offset,
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PIN_FUNC_MASK << field_offset,
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(func & PIN_FUNC_MASK) << field_offset);
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}
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return 0;
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}
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int mvebu_pinctl_probe(struct udevice *dev)
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{
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(dev);
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struct mvebu_pinctrl_priv *priv;
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priv = dev_get_priv(dev);
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if (!priv) {
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debug("%s: Failed to get private\n", __func__);
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return -EINVAL;
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}
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priv->base_reg = dev_read_addr_ptr(dev);
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if (!priv->base_reg) {
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debug("%s: Failed to get base address\n", __func__);
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return -EINVAL;
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}
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priv->pin_cnt = fdtdec_get_int(blob, node, "pin-count",
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MVEBU_MAX_PINS_PER_BANK);
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priv->max_func = fdtdec_get_int(blob, node, "max-func",
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MVEBU_MAX_FUNC);
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priv->bank_name = fdt_getprop(blob, node, "bank-name", NULL);
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priv->reg_direction = 1;
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if (fdtdec_get_bool(blob, node, "reverse-reg"))
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priv->reg_direction = -1;
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return mvebu_pinctrl_set_state_all(dev, dev);
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}
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static struct pinctrl_ops mvebu_pinctrl_ops = {
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.set_state = mvebu_pinctrl_set_state
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};
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static const struct udevice_id mvebu_pinctrl_ids[] = {
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{ .compatible = "marvell,mvebu-pinctrl" },
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{ .compatible = "marvell,ap806-pinctrl" },
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{ .compatible = "marvell,armada-7k-pinctrl" },
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{ .compatible = "marvell,armada-8k-cpm-pinctrl" },
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{ .compatible = "marvell,armada-8k-cps-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_mvebu) = {
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.name = "mvebu_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = mvebu_pinctrl_ids,
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.priv_auto = sizeof(struct mvebu_pinctrl_priv),
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.ops = &mvebu_pinctrl_ops,
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.probe = mvebu_pinctl_probe
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};
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