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7a6577fed4
Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
217 lines
7 KiB
C
217 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx-regs.h>
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#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR + 4 * 0)
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#define CTL_START 0x1
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#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3)
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#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197)
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#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250)
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#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251)
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#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266)
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#define DFI_INIT_COMPLETE 0x2
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#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614)
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#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615)
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#define DENALI_PI_00 (DDR_PI_BASE_ADDR + 4 * 0)
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#define PI_START 0x1
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#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4)
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#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11)
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#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12)
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#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23)
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#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
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#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624)
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#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537)
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#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
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#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
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#define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547)
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#define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555)
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#define DENALI_PHY_1564 (DDR_PHY_BASE_ADDR + 4 * 1564)
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#define DENALI_PHY_1565 (DDR_PHY_BASE_ADDR + 4 * 1565)
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static void ddr_enable_pll_bypass(void)
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{
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u32 reg_val;
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/* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */
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reg_val = readl(DENALI_PI_04) & ~0x1;
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writel(reg_val, DENALI_PI_04);
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/* PI_FREQ_MAP=0x1 (DENALI_PI_12) */
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writel(0x1, DENALI_PI_12);
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/* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */
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reg_val = readl(DENALI_PI_11) & ~(0x1f << 8);
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writel(reg_val, DENALI_PI_11);
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/* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */
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reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24);
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writel(reg_val, DENALI_CTL_23);
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/* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */
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reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8);
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writel(reg_val, DENALI_PHY_1547);
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/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
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reg_val = readl(DENALI_PHY_1624) | 0x1;
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writel(reg_val, DENALI_PHY_1624);
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/* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */
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reg_val = readl(DENALI_PHY_1555) | 0x1;
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writel(reg_val, DENALI_PHY_1555);
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/* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */
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reg_val = 0x020100;
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writel(reg_val, DENALI_CTL_25);
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}
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int ddr_calibration(unsigned int fsp_table[3])
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{
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u32 reg_val;
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u32 int_status_init, phy_freq_req, phy_freq_type;
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u32 lock_0, lock_1, lock_2;
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u32 freq_chg_pt, freq_chg_cnt;
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if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
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ddr_enable_pll_bypass();
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freq_chg_cnt = 0;
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freq_chg_pt = 0;
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} else {
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reg_val = readl(DENALI_CTL_250);
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if (((reg_val >> 16) & 0x3) == 1)
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freq_chg_cnt = 2;
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else
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freq_chg_cnt = 3;
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reg_val = readl(DENALI_PI_12);
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if (reg_val == 0x3) {
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freq_chg_pt = 1;
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} else if (reg_val == 0x7) {
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freq_chg_pt = 2;
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} else {
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printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
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return -1;
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}
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}
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/* Assert PI_START parameter and then assert START parameter in Controller. */
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reg_val = readl(DENALI_PI_00) | PI_START;
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writel(reg_val, DENALI_PI_00);
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reg_val = readl(DENALI_CTL_00) | CTL_START;
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writel(reg_val, DENALI_CTL_00);
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/* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */
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do {
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if (!freq_chg_cnt) {
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int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff;
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/* DDR subsystem is ready for traffic. */
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if (int_status_init & DFI_INIT_COMPLETE) {
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debug("complete\n");
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break;
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}
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}
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/*
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* During leveling, PHY will request for freq change and SoC clock logic
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* should provide requested frequency
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* Polling SIM LPDDR_CTRL2 Bit phy_freq_chg_req until be 1'b1
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*/
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reg_val = readl(AVD_SIM_LPDDR_CTRL2);
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phy_freq_req = (reg_val >> 7) & 0x1;
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if (phy_freq_req) {
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phy_freq_type = reg_val & 0x1F;
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if (phy_freq_type == 0x00) {
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debug("Poll for freq_chg_req on SIM register and change to F0 frequency.\n");
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set_ddr_clk(fsp_table[phy_freq_type] >> 1);
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/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
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reg_val = readl(AVD_SIM_LPDDR_CTRL2);
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writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
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} else if (phy_freq_type == 0x01) {
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debug("Poll for freq_chg_req on SIM register and change to F1 frequency.\n");
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set_ddr_clk(fsp_table[phy_freq_type] >> 1);
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/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
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reg_val = readl(AVD_SIM_LPDDR_CTRL2);
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writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
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if (freq_chg_pt == 1)
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freq_chg_cnt--;
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} else if (phy_freq_type == 0x02) {
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debug("Poll for freq_chg_req on SIM register and change to F2 frequency.\n");
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set_ddr_clk(fsp_table[phy_freq_type] >> 1);
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/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
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reg_val = readl(AVD_SIM_LPDDR_CTRL2);
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writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
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if (freq_chg_pt == 2)
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freq_chg_cnt--;
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}
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reg_val = readl(AVD_SIM_LPDDR_CTRL2);
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}
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} while (1);
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/* Check PLL lock status */
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lock_0 = readl(DENALI_PHY_1564) & 0xffff;
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lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff;
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lock_2 = readl(DENALI_PHY_1565) & 0xffff;
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if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) {
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debug("De-Skew PLL failed to lock\n");
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debug("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2);
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return -1;
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}
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debug("De-Skew PLL is locked and ready\n");
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return 0;
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}
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int ddr_init(struct dram_timing_info2 *dram_timing)
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{
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int i;
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if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
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/* Use PLL bypass for boot freq */
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/* Since PLL can't generate the double freq, Need ddr clock to generate it. */
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set_ddr_clk(dram_timing->fsp_table[0]); /* Set to boot freq */
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setbits_le32(AVD_SIM_BASE_ADDR, 0x1); /* SIM_DDR_CTRL_DIV2_EN */
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} else {
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set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */
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clrbits_le32(AVD_SIM_BASE_ADDR, 0x1); /* SIM_DDR_CTRL_DIV2_EN */
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}
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/* Initialize CTL registers */
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for (i = 0; i < dram_timing->ctl_cfg_num; i++)
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writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);
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/* Initialize PI registers */
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for (i = 0; i < dram_timing->pi_cfg_num; i++)
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writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg);
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/* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */
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writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
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for (i = 0; i < dram_timing->phy_f1_cfg_num; i++)
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writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg);
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/* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */
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writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537);
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for (i = 0; i < dram_timing->phy_f2_cfg_num; i++)
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writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg);
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/* Re-enable MULTICAST mode */
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writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
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return ddr_calibration(dram_timing->fsp_table);
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}
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