mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 13:33:40 +00:00
b092f96290
Add clock tables for R8A779A0 V3U SoC from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
--
Marek: - Add .reset_modemr_offset
- Sync tables from Linux 5.12
- Rebase on latest u-boot
140 lines
3 KiB
C
140 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RCar Gen3 CPG MSSR driver
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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bool renesas_clk_is_mod(struct clk *clk)
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{
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return (clk->id >> 16) == CPG_MOD;
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}
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int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
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const struct mssr_mod_clk **mssr)
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{
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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for (i = 0; i < info->mod_clk_size; i++) {
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if (info->mod_clk[i].id !=
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(info->mod_clk_base + MOD_CLK_PACK(clkid)))
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continue;
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*mssr = &info->mod_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
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const struct cpg_core_clk **core)
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{
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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for (i = 0; i < info->core_clk_size; i++) {
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if (info->core_clk[i].id != clkid)
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continue;
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*core = &info->core_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
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struct clk *parent)
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{
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const struct cpg_core_clk *core;
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const struct mssr_mod_clk *mssr;
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int ret;
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if (renesas_clk_is_mod(clk)) {
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ret = renesas_clk_get_mod(clk, info, &mssr);
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if (ret)
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return ret;
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parent->id = mssr->parent;
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} else {
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ret = renesas_clk_get_core(clk, info, &core);
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if (ret)
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return ret;
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if (core->type == CLK_TYPE_IN)
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parent->id = ~0; /* Top-level clock */
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else
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parent->id = core->parent;
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}
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parent->dev = clk->dev;
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return 0;
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}
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int renesas_clk_endisable(struct clk *clk, void __iomem *base,
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struct cpg_mssr_info *info, bool enable)
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{
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const unsigned long clkid = clk->id & 0xffff;
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const unsigned int reg = clkid / 100;
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const unsigned int bit = clkid % 100;
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const u32 bitmask = BIT(bit);
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if (!renesas_clk_is_mod(clk))
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return -EINVAL;
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debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
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clkid, reg, bit, enable ? "ON" : "OFF");
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if (enable) {
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clrbits_le32(base + info->control_regs[reg], bitmask);
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return wait_for_bit_le32(base + info->status_regs[reg],
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bitmask, 0, 100, 0);
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} else {
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setbits_le32(base + info->control_regs[reg], bitmask);
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return 0;
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}
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}
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int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
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{
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unsigned int i;
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/* Stop TMU0 */
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clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
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/* Stop module clock */
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for (i = 0; i < info->mstp_table_size; i++) {
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clrsetbits_le32(base + info->control_regs[i],
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info->mstp_table[i].sdis,
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info->mstp_table[i].sen);
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if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U)
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continue;
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clrsetbits_le32(base + RMSTPCR(i),
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info->mstp_table[i].rdis,
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info->mstp_table[i].ren);
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}
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return 0;
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}
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