..
base_addr_a10.h
arm: socfpga: Add onchip RAM size macro
2020-03-31 02:52:38 +02:00
base_addr_ac5.h
arm: socfpga: Add onchip RAM size macro
2020-03-31 02:52:38 +02:00
base_addr_s10.h
arm: socfpga: agilex: Add base address for Intel Agilex SoC
2020-01-07 14:38:33 +01:00
boot0.h
ARM: socfpga: Add boot trampoline for Arria10
2018-05-08 21:08:42 +02:00
clock_manager.h
Use __ASSEMBLY__ as the assembly macros
2020-05-18 21:19:23 -04:00
clock_manager_agilex.h
arm: socfpga: agilex: Add clock wrapper functions
2020-01-07 14:38:33 +01:00
clock_manager_arria10.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
clock_manager_gen5.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
clock_manager_s10.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
clock_manager_soc64.h
arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
2020-01-07 14:38:33 +01:00
firewall.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
fpga_manager.h
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00
fpga_manager_arria10.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
fpga_manager_gen5.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
freeze_controller.h
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00
gpio.h
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00
handoff_s10.h
arm: agilex: Add clock handoff offset for Agilex
2020-01-07 14:38:33 +01:00
mailbox_s10.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
misc.h
arm: socfpga: soc64: Check FPGA Config status register before bridge reset
2020-09-03 11:26:07 +08:00
nic301.h
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00
pinmux.h
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00
reset_manager.h
arm: socfpga: agilex: Add reset manager support
2020-01-07 14:38:33 +01:00
reset_manager_arria10.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
reset_manager_gen5.h
arm: socfpga: Convert reset manager from struct to defines
2020-01-07 14:38:33 +01:00
reset_manager_soc64.h
arm: socfpga: Move Stratix10 and Agilex reset manager common code
2020-01-07 14:38:33 +01:00
scan_manager.h
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00
scu.h
ARM: socfpga: Fix Documentation errors in scu_registers
2018-05-18 10:30:47 +02:00
sdram.h
ARM: socfpga: Add DDR driver for Arria 10
2018-05-18 10:30:47 +02:00
sdram_arria10.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
sdram_gen5.h
ddr: altera: Add DDR2 support to Gen5 driver
2020-02-05 03:01:57 +01:00
system_manager.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
system_manager_arria10.h
arm: socfpga: Convert system manager from struct to defines
2020-01-07 14:38:33 +01:00
system_manager_gen5.h
arm: socfpga: Convert system manager from struct to defines
2020-01-07 14:38:33 +01:00
system_manager_soc64.h
arm: socfpga: soc64: Check FPGA Config status register before bridge reset
2020-09-03 11:26:07 +08:00
timer.h
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00