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Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| pci-aardvark.c | ||
| pci-emul-uclass.c | ||
| pci-rcar-gen2.c | ||
| pci-rcar-gen3.c | ||
| pci-uclass.c | ||
| pci_auto.c | ||
| pci_auto_common.c | ||
| pci_common.c | ||
| pci_compat.c | ||
| pci_gt64120.c | ||
| pci_internal.h | ||
| pci_mpc85xx.c | ||
| pci_msc01.c | ||
| pci_mvebu.c | ||
| pci_octeontx.c | ||
| pci_rom.c | ||
| pci_sandbox.c | ||
| pci_sh4.c | ||
| pci_sh7751.c | ||
| pci_sh7780.c | ||
| pci_tegra.c | ||
| pci_x86.c | ||
| pcie_brcmstb.c | ||
| pcie_dw_common.c | ||
| pcie_dw_common.h | ||
| pcie_dw_meson.c | ||
| pcie_dw_mvebu.c | ||
| pcie_dw_rockchip.c | ||
| pcie_dw_sifive.c | ||
| pcie_dw_ti.c | ||
| pcie_ecam_generic.c | ||
| pcie_ecam_synquacer.c | ||
| pcie_fsl.c | ||
| pcie_fsl.h | ||
| pcie_fsl_fixup.c | ||
| pcie_imx.c | ||
| pcie_intel_fpga.c | ||
| pcie_iproc.c | ||
| pcie_layerscape.c | ||
| pcie_layerscape.h | ||
| pcie_layerscape_ep.c | ||
| pcie_layerscape_fixup.c | ||
| pcie_layerscape_fixup_common.c | ||
| pcie_layerscape_fixup_common.h | ||
| pcie_layerscape_gen4.c | ||
| pcie_layerscape_gen4.h | ||
| pcie_layerscape_gen4_fixup.c | ||
| pcie_layerscape_rc.c | ||
| pcie_mediatek.c | ||
| pcie_octeon.c | ||
| pcie_phytium.c | ||
| pcie_rockchip.c | ||
| pcie_uniphier.c | ||
| pcie_xilinx.c | ||