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LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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.. | ||
clock.h | ||
config.h | ||
cpu.h | ||
fdt.h | ||
fsl_icid.h | ||
fsl_portals.h | ||
fsl_serdes.h | ||
immap_lsch2.h | ||
immap_lsch3.h | ||
imx-regs.h | ||
mmu.h | ||
mp.h | ||
ns_access.h | ||
ppa.h | ||
soc.h | ||
speed.h | ||
stream_id_lsch2.h | ||
stream_id_lsch3.h |