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LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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| .. | ||
| doc | ||
| cpu.c | ||
| cpu.h | ||
| fdt.c | ||
| fsl_lsch2_serdes.c | ||
| fsl_lsch2_speed.c | ||
| fsl_lsch3_serdes.c | ||
| fsl_lsch3_speed.c | ||
| icid.c | ||
| Kconfig | ||
| lowlevel.S | ||
| ls1012a_serdes.c | ||
| ls1043_ids.c | ||
| ls1043a_psci.S | ||
| ls1043a_serdes.c | ||
| ls1046_ids.c | ||
| ls1046a_serdes.c | ||
| ls1088a_serdes.c | ||
| ls2080a_serdes.c | ||
| lx2160a_serdes.c | ||
| Makefile | ||
| mp.c | ||
| ppa.c | ||
| soc.c | ||
| spl.c | ||