mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 00:21:06 +00:00
7336278ea2
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
362 lines
7.7 KiB
ArmAsm
362 lines
7.7 KiB
ArmAsm
/*
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* Lowlevel setup for ORIGEN board based on EXYNOS4210
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*
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* Copyright (C) 2011 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/cpu.h>
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#include "origen_setup.h"
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/*
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* Register usages:
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*
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* r5 has zero always
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* r7 has GPIO part1 base 0x11400000
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* r6 has GPIO part2 base 0x11000000
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*/
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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.globl lowlevel_init
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lowlevel_init:
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push {lr}
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/* r5 has always zero */
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mov r5, #0
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ldr r7, =EXYNOS4_GPIO_PART1_BASE
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ldr r6, =EXYNOS4_GPIO_PART2_BASE
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/* check reset status */
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ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
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ldr r1, [r0]
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/* AFTR wakeup reset */
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ldr r2, =S5P_CHECK_DIDLE
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cmp r1, r2
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beq exit_wakeup
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/* LPA wakeup reset */
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ldr r2, =S5P_CHECK_LPA
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cmp r1, r2
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beq exit_wakeup
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/* Sleep wakeup reset */
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ldr r2, =S5P_CHECK_SLEEP
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cmp r1, r2
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beq wakeup_reset
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/*
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* If U-boot is already running in ram, no need to relocate U-Boot.
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* Memory controller must be configured before relocating U-Boot
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* in ram.
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*/
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ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
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bic r1, pc, r0 /* pc <- current addr of code */
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/* r1 <- unmasked bits of pc */
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ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
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bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
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cmp r1, r2 /* compare r1, r2 */
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beq 1f /* r0 == r1 then skip sdram init */
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/* init system clock */
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bl system_clock_init
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/* Memory initialize */
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bl mem_ctrl_asm_init
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1:
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/* for UART */
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bl uart_asm_init
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bl tzpc_init
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pop {pc}
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wakeup_reset:
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bl system_clock_init
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bl mem_ctrl_asm_init
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bl tzpc_init
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exit_wakeup:
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/* Load return address and jump to kernel */
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ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
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/* r1 = physical address of exynos4210_cpu_resume function */
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ldr r1, [r0]
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/* Jump to kernel*/
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mov pc, r1
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nop
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nop
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/*
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* system_clock_init: Initialize core clock and bus clock.
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* void system_clock_init(void)
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*/
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system_clock_init:
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push {lr}
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ldr r0, =EXYNOS4_CLOCK_BASE
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/* APLL(1), MPLL(1), CORE(0), HPM(0) */
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ldr r1, =CLK_SRC_CPU_VAL
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ldr r2, =CLK_SRC_CPU_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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2: subs r1, r1, #1
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bne 2b
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ldr r1, =CLK_SRC_TOP0_VAL
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ldr r2, =CLK_SRC_TOP0_OFFSET
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str r1, [r0, r2]
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ldr r1, =CLK_SRC_TOP1_VAL
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ldr r2, =CLK_SRC_TOP1_OFFSET
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str r1, [r0, r2]
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/* DMC */
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ldr r1, =CLK_SRC_DMC_VAL
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ldr r2, =CLK_SRC_DMC_OFFSET
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str r1, [r0, r2]
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/*CLK_SRC_LEFTBUS */
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ldr r1, =CLK_SRC_LEFTBUS_VAL
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ldr r2, =CLK_SRC_LEFTBUS_OFFSET
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str r1, [r0, r2]
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/*CLK_SRC_RIGHTBUS */
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ldr r1, =CLK_SRC_RIGHTBUS_VAL
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ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
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str r1, [r0, r2]
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/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
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ldr r1, =CLK_SRC_FSYS_VAL
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ldr r2, =CLK_SRC_FSYS_OFFSET
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str r1, [r0, r2]
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/* UART[0:4] */
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ldr r1, =CLK_SRC_PERIL0_VAL
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ldr r2, =CLK_SRC_PERIL0_OFFSET
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str r1, [r0, r2]
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/* FIMD0 */
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ldr r1, =CLK_SRC_LCD0_VAL
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ldr r2, =CLK_SRC_LCD0_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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3: subs r1, r1, #1
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bne 3b
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/* CLK_DIV_CPU0 */
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ldr r1, =CLK_DIV_CPU0_VAL
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ldr r2, =CLK_DIV_CPU0_OFFSET
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str r1, [r0, r2]
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/* CLK_DIV_CPU1 */
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ldr r1, =CLK_DIV_CPU1_VAL
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ldr r2, =CLK_DIV_CPU1_OFFSET
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str r1, [r0, r2]
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/* CLK_DIV_DMC0 */
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ldr r1, =CLK_DIV_DMC0_VAL
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ldr r2, =CLK_DIV_DMC0_OFFSET
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str r1, [r0, r2]
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/*CLK_DIV_DMC1 */
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ldr r1, =CLK_DIV_DMC1_VAL
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ldr r2, =CLK_DIV_DMC1_OFFSET
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str r1, [r0, r2]
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/* CLK_DIV_LEFTBUS */
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ldr r1, =CLK_DIV_LEFTBUS_VAL
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ldr r2, =CLK_DIV_LEFTBUS_OFFSET
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str r1, [r0, r2]
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/* CLK_DIV_RIGHTBUS */
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ldr r1, =CLK_DIV_RIGHTBUS_VAL
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ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
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str r1, [r0, r2]
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/* CLK_DIV_TOP */
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ldr r1, =CLK_DIV_TOP_VAL
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ldr r2, =CLK_DIV_TOP_OFFSET
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str r1, [r0, r2]
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/* MMC[0:1] */
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ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */
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ldr r2, =CLK_DIV_FSYS1_OFFSET
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str r1, [r0, r2]
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/* MMC[2:3] */
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ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */
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ldr r2, =CLK_DIV_FSYS2_OFFSET
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str r1, [r0, r2]
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/* MMC4 */
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ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */
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ldr r2, =CLK_DIV_FSYS3_OFFSET
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str r1, [r0, r2]
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/* CLK_DIV_PERIL0: UART Clock Divisors */
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ldr r1, =CLK_DIV_PERIL0_VAL
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ldr r2, =CLK_DIV_PERIL0_OFFSET
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str r1, [r0, r2]
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/* Set PLL locktime */
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ldr r1, =PLL_LOCKTIME
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ldr r2, =APLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =PLL_LOCKTIME
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ldr r2, =MPLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =PLL_LOCKTIME
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ldr r2, =EPLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =PLL_LOCKTIME
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ldr r2, =VPLL_LOCK_OFFSET
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str r1, [r0, r2]
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/* APLL_CON1 */
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ldr r1, =APLL_CON1_VAL
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ldr r2, =APLL_CON1_OFFSET
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str r1, [r0, r2]
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/* APLL_CON0 */
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ldr r1, =APLL_CON0_VAL
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ldr r2, =APLL_CON0_OFFSET
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str r1, [r0, r2]
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/* MPLL_CON1 */
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ldr r1, =MPLL_CON1_VAL
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ldr r2, =MPLL_CON1_OFFSET
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str r1, [r0, r2]
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/* MPLL_CON0 */
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ldr r1, =MPLL_CON0_VAL
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ldr r2, =MPLL_CON0_OFFSET
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str r1, [r0, r2]
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/* EPLL */
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ldr r1, =EPLL_CON1_VAL
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ldr r2, =EPLL_CON1_OFFSET
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str r1, [r0, r2]
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/* EPLL_CON0 */
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ldr r1, =EPLL_CON0_VAL
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ldr r2, =EPLL_CON0_OFFSET
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str r1, [r0, r2]
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/* VPLL_CON1 */
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ldr r1, =VPLL_CON1_VAL
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ldr r2, =VPLL_CON1_OFFSET
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str r1, [r0, r2]
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/* VPLL_CON0 */
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ldr r1, =VPLL_CON0_VAL
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ldr r2, =VPLL_CON0_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x30000
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4: subs r1, r1, #1
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bne 4b
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pop {pc}
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/*
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* uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
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* void uart_asm_init(void)
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*/
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.globl uart_asm_init
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uart_asm_init:
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/* setup UART0-UART3 GPIOs (part1) */
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mov r0, r7
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ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
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str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
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ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
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str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
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ldr r0, =EXYNOS4_UART_BASE
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add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
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ldr r1, =ULCON_VAL
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str r1, [r0, #ULCON_OFFSET]
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ldr r1, =UCON_VAL
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str r1, [r0, #UCON_OFFSET]
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ldr r1, =UFCON_VAL
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str r1, [r0, #UFCON_OFFSET]
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ldr r1, =UBRDIV_VAL
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str r1, [r0, #UBRDIV_OFFSET]
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ldr r1, =UFRACVAL_VAL
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str r1, [r0, #UFRACVAL_OFFSET]
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mov pc, lr
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nop
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nop
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nop
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/* Setting TZPC[TrustZone Protection Controller] */
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tzpc_init:
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ldr r0, =TZPC0_BASE
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mov r1, #R0SIZE
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str r1, [r0]
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mov r1, #DECPROTXSET
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC1_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC2_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC3_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC4_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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ldr r0, =TZPC5_BASE
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str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
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str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
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mov pc, lr
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