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Origen: Select SCLKMPLL as FIMD0 parent clock
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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2 changed files with 17 additions and 0 deletions
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@ -158,6 +158,11 @@ system_clock_init:
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ldr r2, =CLK_SRC_PERIL0_OFFSET
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str r1, [r0, r2]
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/* FIMD0 */
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ldr r1, =CLK_SRC_LCD0_VAL
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ldr r2, =CLK_SRC_LCD0_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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3: subs r1, r1, #1
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@ -56,6 +56,8 @@
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#define CLK_SRC_PERIL0_OFFSET 0xC250
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#define CLK_DIV_PERIL0_OFFSET 0xC550
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#define CLK_SRC_LCD0_OFFSET 0xC234
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#define APLL_LOCK_OFFSET 0x14000
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#define MPLL_LOCK_OFFSET 0x14008
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#define APLL_CON0_OFFSET 0x14100
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@ -351,6 +353,16 @@
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| (UART1_RATIO << 4) \
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| (UART0_RATIO << 0))
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/* CLK_SRC_LCD0 */
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#define FIMD_SEL_SCLKMPLL 6
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#define MDNIE0_SEL_XUSBXTI 1
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#define MDNIE_PWM0_SEL_XUSBXTI 1
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#define MIPI0_SEL_XUSBXTI 1
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#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
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| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
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| (MDNIE0_SEL_XUSBXTI << 4) \
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| (FIMD_SEL_SCLKMPLL << 0))
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/* Required period to generate a stable clock output */
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/* PLL_LOCK_TIME */
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#define PLL_LOCKTIME 0x1C20
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