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Origen: Select SCLKMPLL as FIMD0 parent clock

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Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Chander Kashyap 2011-12-18 20:16:32 +00:00 committed by Albert ARIBAUD
parent db68bc2c2d
commit 7336278ea2
2 changed files with 17 additions and 0 deletions
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5
board/samsung/origen/lowlevel_init.S
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@ -158,6 +158,11 @@ system_clock_init:
ldr r2, =CLK_SRC_PERIL0_OFFSET
str r1, [r0, r2]
/* FIMD0 */
ldr r1, =CLK_SRC_LCD0_VAL
ldr r2, =CLK_SRC_LCD0_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
3: subs r1, r1, #1

12
board/samsung/origen/origen_setup.h
View file

@ -56,6 +56,8 @@
#define CLK_SRC_PERIL0_OFFSET 0xC250
#define CLK_DIV_PERIL0_OFFSET 0xC550
#define CLK_SRC_LCD0_OFFSET 0xC234
#define APLL_LOCK_OFFSET 0x14000
#define MPLL_LOCK_OFFSET 0x14008
#define APLL_CON0_OFFSET 0x14100
@ -351,6 +353,16 @@
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
/* CLK_SRC_LCD0 */
#define FIMD_SEL_SCLKMPLL 6
#define MDNIE0_SEL_XUSBXTI 1
#define MDNIE_PWM0_SEL_XUSBXTI 1
#define MIPI0_SEL_XUSBXTI 1
#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
| (MDNIE0_SEL_XUSBXTI << 4) \
| (FIMD_SEL_SCLKMPLL << 0))
/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x1C20