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ee31be429b
The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_STRUCTS_IF_H
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#define LPDDR4_STRUCTS_IF_H
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#include <linux/types.h>
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#include "lpddr4_if.h"
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struct lpddr4_config_s {
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struct lpddr4_ctlregs_s *ctlbase;
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lpddr4_infocallback infohandler;
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lpddr4_ctlcallback ctlinterrupthandler;
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lpddr4_phyindepcallback phyindepinterrupthandler;
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};
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struct lpddr4_privatedata_s {
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struct lpddr4_ctlregs_s *ctlbase;
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lpddr4_infocallback infohandler;
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lpddr4_ctlcallback ctlinterrupthandler;
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lpddr4_phyindepcallback phyindepinterrupthandler;
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void *ddr_instance;
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};
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struct lpddr4_debuginfo_s {
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u8 pllerror;
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u8 iocaliberror;
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u8 rxoffseterror;
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u8 catraingerror;
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u8 wrlvlerror;
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u8 gatelvlerror;
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u8 readlvlerror;
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u8 dqtrainingerror;
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};
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struct lpddr4_fspmoderegs_s {
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u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
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};
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#endif /* LPDDR4_STRUCTS_IF_H */
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