Tom Rini 44fb0d6c9f Xilinx/FPGA changes for v2020.01 ... FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXZ2mcwAKCRDKSWXLKUoM IT/KAJ4tL49YwINqCVGd7gafWvdfC4htygCcCgr9gLnJ+LjDQkxWT/r6faIcL00= =OnMk -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file		2019-10-09 16:22:03 -04:00
..
arc	NET: DW: fix regression for ARC boards	2019-10-07 13:23:49 -04:00
arm	Xilinx/FPGA changes for v2020.01	2019-10-09 16:22:03 -04:00
m68k	env: Drop environment.h header file where not needed	2019-08-11 16:43:41 -04:00
microblaze	microblaze: Setup initrd_high and fdt_high at run time	2019-10-08 09:55:11 +02:00
mips	env: Move env_init() to env.h	2019-08-11 16:43:41 -04:00
nds32	env: Drop environment.h header file where not needed	2019-08-11 16:43:41 -04:00
nios2	.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore	2018-06-18 14:43:12 -04:00
powerpc	MPC8548: dts: Added PCIe DT node	2019-08-28 13:47:47 +05:30
riscv	riscv: cache: use CCTL to flush d-cache	2019-09-03 09:31:03 +08:00
sandbox	sandbox: pci: Create a new sandbox_pci_read_bar() function	2019-10-08 13:57:48 +08:00
sh	sh: r2dplus: Fix missing PCI range	2019-09-14 21:28:55 +02:00
x86	x86: Use mtrr_commit() with FSP2	2019-10-08 13:57:49 +08:00
xtensa	env: Move env_get() to env.h	2019-08-11 16:43:41 -04:00
.gitignore
Kconfig	sh: r2dplus: Enable OF control	2019-09-02 17:38:43 +02:00