Rick Chen 444c46413f riscv: Fix clear bss loop in the start-up code ... For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>		2019-12-10 08:23:10 +08:00
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ax25	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	2019-12-10 08:23:10 +08:00
generic	common: Move board_get_usable_ram_top() out of common.h	2019-12-02 18:25:04 -05:00
cpu.c	riscv: add run mode configuration for SPL	2019-08-26 16:07:42 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Return to previous privilege level after trap handling	2018-12-18 09:56:27 +08:00
start.S	riscv: Fix clear bss loop in the start-up code	2019-12-10 08:23:10 +08:00
u-boot-spl.lds	riscv: Fix clear bss loop in the start-up code	2019-12-10 08:23:10 +08:00
u-boot.lds	riscv: Fix clear bss loop in the start-up code	2019-12-10 08:23:10 +08:00