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https://github.com/AsahiLinux/u-boot
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624 lines
16 KiB
C
624 lines
16 KiB
C
/*
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* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Based vaguely on the pxa mmc code:
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <part.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct fsl_esdhc {
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uint dsaddr;
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uint blkattr;
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uint cmdarg;
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uint xfertyp;
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uint cmdrsp0;
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uint cmdrsp1;
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uint cmdrsp2;
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uint cmdrsp3;
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uint datport;
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uint prsstat;
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uint proctl;
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uint sysctl;
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uint irqstat;
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uint irqstaten;
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uint irqsigen;
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uint autoc12err;
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uint hostcapblt;
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uint wml;
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uint mixctrl;
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char reserved1[4];
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uint fevt;
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char reserved2[168];
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uint hostver;
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char reserved3[780];
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uint scr;
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};
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/* Return the XFERTYP flags for a given command and data packet */
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static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
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{
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uint xfertyp = 0;
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if (data) {
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xfertyp |= XFERTYP_DPSEL;
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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xfertyp |= XFERTYP_DMAEN;
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#endif
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if (data->blocks > 1) {
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xfertyp |= XFERTYP_MSBSEL;
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xfertyp |= XFERTYP_BCEN;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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xfertyp |= XFERTYP_AC12EN;
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#endif
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}
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if (data->flags & MMC_DATA_READ)
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xfertyp |= XFERTYP_DTDSEL;
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}
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if (cmd->resp_type & MMC_RSP_CRC)
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xfertyp |= XFERTYP_CCCEN;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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xfertyp |= XFERTYP_CICEN;
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if (cmd->resp_type & MMC_RSP_136)
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xfertyp |= XFERTYP_RSPTYP_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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xfertyp |= XFERTYP_RSPTYP_48_BUSY;
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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xfertyp |= XFERTYP_RSPTYP_48;
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#ifdef CONFIG_MX53
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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xfertyp |= XFERTYP_CMDTYP_ABORT;
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#endif
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return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
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}
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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/*
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* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
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*/
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static void
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esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
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{
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struct fsl_esdhc_cfg *cfg = mmc->priv;
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struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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uint blocks;
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char *buffer;
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uint databuf;
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uint size;
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uint irqstat;
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uint timeout;
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if (data->flags & MMC_DATA_READ) {
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blocks = data->blocks;
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buffer = data->dest;
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while (blocks) {
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timeout = PIO_TIMEOUT;
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size = data->blocksize;
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irqstat = esdhc_read32(®s->irqstat);
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while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
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&& --timeout);
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if (timeout <= 0) {
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printf("\nData Read Failed in PIO Mode.");
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return;
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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irqstat = esdhc_read32(®s->irqstat);
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databuf = in_le32(®s->datport);
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*((uint *)buffer) = databuf;
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buffer += 4;
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size -= 4;
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}
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blocks--;
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}
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} else {
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blocks = data->blocks;
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buffer = (char *)data->src;
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while (blocks) {
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timeout = PIO_TIMEOUT;
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size = data->blocksize;
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irqstat = esdhc_read32(®s->irqstat);
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while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
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&& --timeout);
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if (timeout <= 0) {
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printf("\nData Write Failed in PIO Mode.");
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return;
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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databuf = *((uint *)buffer);
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buffer += 4;
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size -= 4;
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irqstat = esdhc_read32(®s->irqstat);
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out_le32(®s->datport, databuf);
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}
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blocks--;
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}
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}
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}
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#endif
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static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
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{
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int timeout;
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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uint wml_value;
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wml_value = data->blocksize/4;
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if (data->flags & MMC_DATA_READ) {
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if (wml_value > WML_RD_WML_MAX)
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wml_value = WML_RD_WML_MAX_VAL;
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esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
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esdhc_write32(®s->dsaddr, (u32)data->dest);
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} else {
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flush_dcache_range((ulong)data->src,
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(ulong)data->src+data->blocks
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*data->blocksize);
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if (wml_value > WML_WR_WML_MAX)
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wml_value = WML_WR_WML_MAX_VAL;
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if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
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printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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return TIMEOUT;
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}
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esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
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wml_value << 16);
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esdhc_write32(®s->dsaddr, (u32)data->src);
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}
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#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
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if (!(data->flags & MMC_DATA_READ)) {
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if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
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printf("\nThe SD card is locked. "
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"Can not write to a locked card.\n\n");
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return TIMEOUT;
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}
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esdhc_write32(®s->dsaddr, (u32)data->src);
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} else
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esdhc_write32(®s->dsaddr, (u32)data->dest);
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#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
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esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
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/* Calculate the timeout period for data transactions */
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/*
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* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
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* 2)Timeout period should be minimum 0.250sec as per SD Card spec
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* So, Number of SD Clock cycles for 0.25sec should be minimum
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* (SD Clock/sec * 0.25 sec) SD Clock cycles
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* = (mmc->tran_speed * 1/4) SD Clock cycles
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* As 1) >= 2)
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* => (2^(timeout+13)) >= mmc->tran_speed * 1/4
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* Taking log2 both the sides
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* => timeout + 13 >= log2(mmc->tran_speed/4)
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* Rounding up to next power of 2
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* => timeout + 13 = log2(mmc->tran_speed/4) + 1
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* => timeout + 13 = fls(mmc->tran_speed/4)
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*/
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timeout = fls(mmc->tran_speed/4);
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timeout -= 13;
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if (timeout > 14)
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timeout = 14;
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if (timeout < 0)
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timeout = 0;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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if ((timeout == 4) || (timeout == 8) || (timeout == 12))
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timeout++;
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#endif
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esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
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return 0;
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}
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static void check_and_invalidate_dcache_range
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(struct mmc_cmd *cmd,
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struct mmc_data *data) {
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unsigned start = (unsigned)data->dest ;
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unsigned size = roundup(ARCH_DMA_MINALIGN,
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data->blocks*data->blocksize);
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unsigned end = start+size ;
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invalidate_dcache_range(start, end);
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}
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/*
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* Sends a command out on the bus. Takes the mmc pointer,
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* a command pointer, and an optional data pointer.
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*/
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static int
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esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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uint xfertyp;
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uint irqstat;
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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return 0;
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#endif
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esdhc_write32(®s->irqstat, -1);
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sync();
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/* Wait for the bus to be idle */
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while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
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(esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
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;
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while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
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;
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/* Wait at least 8 SD clock cycles before the next command */
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/*
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* Note: This is way more than 8 cycles, but 1ms seems to
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* resolve timing issues with some cards
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*/
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udelay(1000);
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/* Set up for a data transfer if we have one */
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if (data) {
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int err;
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err = esdhc_setup_data(mmc, data);
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if(err)
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return err;
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}
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/* Figure out the transfer arguments */
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xfertyp = esdhc_xfertyp(cmd, data);
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/* Send the command */
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esdhc_write32(®s->cmdarg, cmd->cmdarg);
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#if defined(CONFIG_FSL_USDHC)
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esdhc_write32(®s->mixctrl,
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(esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
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esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
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#else
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esdhc_write32(®s->xfertyp, xfertyp);
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#endif
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/* Mask all irqs */
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esdhc_write32(®s->irqsigen, 0);
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/* Wait for the command to complete */
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while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
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;
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if (data && (data->flags & MMC_DATA_READ))
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check_and_invalidate_dcache_range(cmd, data);
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irqstat = esdhc_read32(®s->irqstat);
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esdhc_write32(®s->irqstat, irqstat);
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/* Reset CMD and DATA portions on error */
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if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
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esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
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SYSCTL_RSTC);
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while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
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;
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if (data) {
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esdhc_write32(®s->sysctl,
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esdhc_read32(®s->sysctl) |
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SYSCTL_RSTD);
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while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
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;
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}
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}
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if (irqstat & CMD_ERR)
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return COMM_ERR;
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if (irqstat & IRQSTAT_CTOE)
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return TIMEOUT;
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/* Workaround for ESDHC errata ENGcm03648 */
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if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
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int timeout = 2500;
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/* Poll on DATA0 line for cmd with busy signal for 250 ms */
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while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
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PRSSTAT_DAT0)) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0) {
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printf("Timeout waiting for DAT0 to go high!\n");
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return TIMEOUT;
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}
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}
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/* Copy the response to the response buffer */
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if (cmd->resp_type & MMC_RSP_136) {
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u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
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cmdrsp3 = esdhc_read32(®s->cmdrsp3);
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cmdrsp2 = esdhc_read32(®s->cmdrsp2);
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cmdrsp1 = esdhc_read32(®s->cmdrsp1);
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cmdrsp0 = esdhc_read32(®s->cmdrsp0);
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cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
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cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
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cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
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cmd->response[3] = (cmdrsp0 << 8);
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} else
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cmd->response[0] = esdhc_read32(®s->cmdrsp0);
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/* Wait until all of the blocks are transferred */
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if (data) {
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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esdhc_pio_read_write(mmc, data);
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#else
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do {
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irqstat = esdhc_read32(®s->irqstat);
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if (irqstat & IRQSTAT_DTOE)
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return TIMEOUT;
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if (irqstat & DATA_ERR)
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return COMM_ERR;
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} while (!(irqstat & IRQSTAT_TC) &&
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(esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
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#endif
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}
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esdhc_write32(®s->irqstat, -1);
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return 0;
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}
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static void set_sysctl(struct mmc *mmc, uint clock)
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{
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int div, pre_div;
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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int sdhc_clk = cfg->sdhc_clk;
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uint clk;
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if (clock < mmc->f_min)
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clock = mmc->f_min;
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if (sdhc_clk / 16 > clock) {
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for (pre_div = 2; pre_div < 256; pre_div *= 2)
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if ((sdhc_clk / pre_div) <= (clock * 16))
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break;
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} else
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pre_div = 2;
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for (div = 1; div <= 16; div++)
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if ((sdhc_clk / (div * pre_div)) <= clock)
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break;
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pre_div >>= 1;
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div -= 1;
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clk = (pre_div << 8) | (div << 4);
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esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
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esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
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udelay(10000);
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clk = SYSCTL_PEREN | SYSCTL_CKEN;
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esdhc_setbits32(®s->sysctl, clk);
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}
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static void esdhc_set_ios(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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/* Set the clock speed */
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set_sysctl(mmc, mmc->clock);
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/* Set the bus width */
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esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
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if (mmc->bus_width == 4)
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esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
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else if (mmc->bus_width == 8)
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esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
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}
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static int esdhc_init(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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int timeout = 1000;
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/* Reset the entire host controller */
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esdhc_write32(®s->sysctl, SYSCTL_RSTA);
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/* Wait until the controller is available */
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while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
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udelay(1000);
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#ifndef ARCH_MXC
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/* Enable cache snooping */
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esdhc_write32(®s->scr, 0x00000040);
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#endif
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esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
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|
|
/* Set the initial clock speed */
|
|
mmc_set_clock(mmc, 400000);
|
|
|
|
/* Disable the BRR and BWR bits in IRQSTAT */
|
|
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
|
|
|
|
/* Put the PROCTL reg back to the default */
|
|
esdhc_write32(®s->proctl, PROCTL_INIT);
|
|
|
|
/* Set timout to the maximum value */
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int esdhc_getcd(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
int timeout = 1000;
|
|
|
|
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
|
|
udelay(1000);
|
|
|
|
return timeout > 0;
|
|
}
|
|
|
|
static void esdhc_reset(struct fsl_esdhc *regs)
|
|
{
|
|
unsigned long timeout = 100; /* wait max 100 ms */
|
|
|
|
/* reset the controller */
|
|
esdhc_write32(®s->sysctl, SYSCTL_RSTA);
|
|
|
|
/* hardware clears the bit when it is done */
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
|
|
udelay(1000);
|
|
if (!timeout)
|
|
printf("MMC/SD: Reset never completed.\n");
|
|
}
|
|
|
|
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
|
|
{
|
|
struct fsl_esdhc *regs;
|
|
struct mmc *mmc;
|
|
u32 caps, voltage_caps;
|
|
|
|
if (!cfg)
|
|
return -1;
|
|
|
|
mmc = malloc(sizeof(struct mmc));
|
|
|
|
sprintf(mmc->name, "FSL_SDHC");
|
|
regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
|
|
/* First reset the eSDHC controller */
|
|
esdhc_reset(regs);
|
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
|
|
| SYSCTL_IPGEN | SYSCTL_CKEN);
|
|
|
|
mmc->priv = cfg;
|
|
mmc->send_cmd = esdhc_send_cmd;
|
|
mmc->set_ios = esdhc_set_ios;
|
|
mmc->init = esdhc_init;
|
|
mmc->getcd = esdhc_getcd;
|
|
|
|
voltage_caps = 0;
|
|
caps = regs->hostcapblt;
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
|
|
caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
|
|
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
|
|
#endif
|
|
if (caps & ESDHC_HOSTCAPBLT_VS18)
|
|
voltage_caps |= MMC_VDD_165_195;
|
|
if (caps & ESDHC_HOSTCAPBLT_VS30)
|
|
voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
|
|
if (caps & ESDHC_HOSTCAPBLT_VS33)
|
|
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
#ifdef CONFIG_SYS_SD_VOLTAGE
|
|
mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
|
|
#else
|
|
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
#endif
|
|
if ((mmc->voltages & voltage_caps) == 0) {
|
|
printf("voltage not supported by controller\n");
|
|
return -1;
|
|
}
|
|
|
|
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
|
|
|
if (caps & ESDHC_HOSTCAPBLT_HSS)
|
|
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
|
|
mmc->f_min = 400000;
|
|
mmc->f_max = MIN(gd->sdhc_clk, 52000000);
|
|
|
|
mmc->b_max = 0;
|
|
mmc_register(mmc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int fsl_esdhc_mmc_init(bd_t *bis)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg;
|
|
|
|
cfg = malloc(sizeof(struct fsl_esdhc_cfg));
|
|
memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
|
|
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
|
|
cfg->sdhc_clk = gd->sdhc_clk;
|
|
return fsl_esdhc_initialize(bis, cfg);
|
|
}
|
|
|
|
#ifdef CONFIG_OF_LIBFDT
|
|
void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
|
{
|
|
const char *compat = "fsl,esdhc";
|
|
|
|
#ifdef CONFIG_FSL_ESDHC_PIN_MUX
|
|
if (!hwconfig("esdhc")) {
|
|
do_fixup_by_compat(blob, compat, "status", "disabled",
|
|
8 + 1, 1);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
|
|
gd->sdhc_clk, 1);
|
|
|
|
do_fixup_by_compat(blob, compat, "status", "okay",
|
|
4 + 1, 1);
|
|
}
|
|
#endif
|