mirror of
https://github.com/AsahiLinux/u-boot
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06ddcfc95a
This value is only referenced by PowerPC code in a way other than directly as CONFIG_SYS_INIT_SP_ADDR. Switch to CONFIG_SYS_INIT_SP_ADDR directly. Signed-off-by: Tom Rini <trini@konsulko.com>
246 lines
6.6 KiB
C
246 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration settings for the Sentec Cobra Board.
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*
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* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*/
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/*
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* configuration for ASTRO "Urmel" board.
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* Originating from Cobra5272 configuration, messed up by
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* Wolfgang Wegner <w.wegner@astro-kom.de>
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* Please do not bother the original author with bug reports
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* concerning this file.
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*/
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#ifndef _CONFIG_ASTRO_MCF5373L_H
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#define _CONFIG_ASTRO_MCF5373L_H
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#include <linux/stringify.h>
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/*
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* set the card type to actually compile for; either of
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* the possibilities listed below has to be used!
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*/
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#define ASTRO_V532 1
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#if ASTRO_V532
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#define ASTRO_ID 0xF8
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#elif ASTRO_V512
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#define ASTRO_ID 0xFA
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#elif ASTRO_TWIN7S2
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#define ASTRO_ID 0xF9
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#elif ASTRO_V912
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#define ASTRO_ID 0xFC
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#elif ASTRO_COFDMDUOS2
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#define ASTRO_ID 0xFB
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#else
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#error No card type defined!
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#endif
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/*
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* CONFIG_RAM defines if u-boot is loaded via BDM (or started from
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* a different bootloader that has already performed RAM setup) or
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* started directly from flash, which is the regular case for production
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* boards.
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*/
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#ifdef CONFIG_RAM
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#define CONFIG_MONITOR_IS_IN_RAM
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#define ENABLE_JFFS 0
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#else
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#define ENABLE_JFFS 1
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#endif
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/* I2C */
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/*
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* Defines processor clock - important for correct timings concerning serial
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* interface etc.
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*/
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#define CONFIG_SYS_CLK 80000000
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#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
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#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
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#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000
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#define CONFIG_SYS_CORE_SRAM 0x80000000
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#define CONFIG_SYS_UNIFY_CACHE
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/*
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* Define baudrate for UART1 (console output, tftp, ...)
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* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
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* CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
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* in u-boot command interface
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*/
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#define CONFIG_SYS_UART_PORT (2)
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#define CONFIG_SYS_UART2_ALT3_GPIO
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/*
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* Watchdog configuration; Watchdog is disabled for running from RAM
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* and set to highest possible value else. Beware there is no check
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* in the watchdog code to validate the timeout value set here!
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */
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#endif
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/*
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* Configuration for environment
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* Environment is located in the last sector of the flash
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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#else
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/*
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* environment in RAM - This is used to use a single PC-based application
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* to load an image, load U-Boot, load an environment and then start U-Boot
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* to execute the commands from the environment. Feedback is done via setting
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* and reading memory locations.
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*/
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#endif
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/* here we put our FPGA configuration... */
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/* Define user parameters that have to be customized most likely */
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/* AUTOBOOT settings - booting images automatically by u-boot after power on */
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/*
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* The following settings will be contained in the environment block ; if you
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* want to use a neutral environment all those settings can be manually set in
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* u-boot: 'set' command
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loaderversion=11\0" \
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"card_id="__stringify(ASTRO_ID)"\0" \
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"alterafile=0\0" \
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"xilinxfile=0\0" \
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"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
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"fpga load 0 0x41000000 $filesize\0" \
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"alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
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"fpga load 1 0x41000000 $filesize\0" \
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"env_default=1\0" \
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"env_check=if test $env_default -eq 1;"\
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" then setenv env_default 0;saveenv;fi\0"
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/*
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* "update" is a non-standard command that has to be supplied
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* by external update.c; This is not included in mainline because
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* it needs non-blocking CFI routines.
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*/
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#define CONFIG_FPGA_COUNT 1
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#define CONFIG_SYS_FPGA_PROG_FEEDBACK
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#define CONFIG_SYS_FPGA_WAIT 1000
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/* End of user parameters to be customized */
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/* Defines memory range for test */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/* Base register address */
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#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
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/* System Conf. Reg. & System Protection Reg. */
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#define CONFIG_SYS_SCR 0x0003;
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#define CONFIG_SYS_SPR 0xffff;
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/*
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* Definitions for initial stack pointer and data area (in internal SRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
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#define CONFIG_SYS_INIT_RAM_CTRL 0x221
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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/*
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* Chipselect bank definitions
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*
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* CS0 - Flash 32MB (first 16MB)
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* CS1 - Flash 32MB (second half)
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* CS2 - FPGA
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* CS3 - FPGA
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* CS4 - unused
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* CS5 - unused
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*/
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#define CONFIG_SYS_CS0_BASE 0
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#define CONFIG_SYS_CS0_MASK 0x00ff0001
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#define CONFIG_SYS_CS0_CTRL 0x00001fc0
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#define CONFIG_SYS_CS1_BASE 0x01000000
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#define CONFIG_SYS_CS1_MASK 0x00ff0001
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#define CONFIG_SYS_CS1_CTRL 0x00001fc0
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#define CONFIG_SYS_CS2_BASE 0x20000000
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#define CONFIG_SYS_CS2_MASK 0x00ff0001
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#define CONFIG_SYS_CS2_CTRL 0x0000fec0
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#define CONFIG_SYS_CS3_BASE 0x21000000
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#define CONFIG_SYS_CS3_MASK 0x00ff0001
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#define CONFIG_SYS_CS3_CTRL 0x0000fec0
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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/* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
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(CONFIG_SYS_SDRAM_SIZE << 20))
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/* FLASH organization */
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#define CONFIG_SYS_MAX_FLASH_SECT 259
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#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
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#define CONFIG_SYS_FLASH_SIZE 0x2000000
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#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text*)
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#if ENABLE_JFFS
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/* JFFS Partition offset set */
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#define CONFIG_SYS_JFFS2_FIRST_BANK 0
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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/* 512k reserved for u-boot */
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#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40
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#endif
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/* Cache Configuration */
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
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#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
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CF_CACR_DCM_P)
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#endif /* _CONFIG_ASTRO_MCF5373L_H */
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