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0ae7653128
Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
136 lines
3 KiB
ArmAsm
136 lines
3 KiB
ArmAsm
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* This file is based on sample code from ARMv8 ARM.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <linux/linkage.h>
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/*
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* void __asm_flush_dcache_level(level)
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*
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* clean and invalidate one level cache.
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*
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* x0: cache level
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* x1~x9: clobbered
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*/
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ENTRY(__asm_flush_dcache_level)
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lsl x1, x0, #1
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msr csselr_el1, x1 /* select cache level */
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isb /* sync change of cssidr_el1 */
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mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
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and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
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add x2, x2, #4 /* x2 <- log2(cache line size) */
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mov x3, #0x3ff
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and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
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add w4, w3, w3
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sub w4, w4, 1 /* round up log2(#ways + 1) */
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clz w5, w4 /* bit position of #ways */
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mov x4, #0x7fff
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and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
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/* x1 <- cache level << 1 */
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/* x2 <- line length offset */
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/* x3 <- number of cache ways - 1 */
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/* x4 <- number of cache sets - 1 */
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/* x5 <- bit position of #ways */
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loop_set:
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mov x6, x3 /* x6 <- working copy of #ways */
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loop_way:
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lsl x7, x6, x5
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orr x9, x1, x7 /* map way and level to cisw value */
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lsl x7, x4, x2
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orr x9, x9, x7 /* map set number to cisw value */
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dc cisw, x9 /* clean & invalidate by set/way */
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subs x6, x6, #1 /* decrement the way */
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b.ge loop_way
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subs x4, x4, #1 /* decrement the set */
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b.ge loop_set
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ret
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ENDPROC(__asm_flush_dcache_level)
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/*
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* void __asm_flush_dcache_all(void)
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*
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* clean and invalidate all data cache by SET/WAY.
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*/
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ENTRY(__asm_flush_dcache_all)
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dsb sy
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mrs x10, clidr_el1 /* read clidr_el1 */
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lsr x11, x10, #24
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and x11, x11, #0x7 /* x11 <- loc */
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cbz x11, finished /* if loc is 0, exit */
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mov x15, lr
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mov x0, #0 /* start flush at cache level 0 */
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/* x0 <- cache level */
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/* x10 <- clidr_el1 */
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/* x11 <- loc */
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/* x15 <- return address */
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loop_level:
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lsl x1, x0, #1
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add x1, x1, x0 /* x0 <- tripled cache level */
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lsr x1, x10, x1
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and x1, x1, #7 /* x1 <- cache type */
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cmp x1, #2
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b.lt skip /* skip if no cache or icache */
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bl __asm_flush_dcache_level
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skip:
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add x0, x0, #1 /* increment cache level */
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cmp x11, x0
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b.gt loop_level
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mov x0, #0
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msr csselr_el1, x0 /* resotre csselr_el1 */
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dsb sy
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isb
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mov lr, x15
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finished:
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ret
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ENDPROC(__asm_flush_dcache_all)
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/*
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* void __asm_flush_dcache_range(start, end)
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*
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* clean & invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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ENTRY(__asm_flush_dcache_range)
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mrs x3, ctr_el0
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lsr x3, x3, #16
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and x3, x3, #0xf
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc civac, x0 /* clean & invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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ENDPROC(__asm_flush_dcache_range)
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/*
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* void __asm_invalidate_icache_all(void)
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*
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* invalidate all tlb entries.
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*/
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ENTRY(__asm_invalidate_icache_all)
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ic ialluis
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isb sy
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ret
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ENDPROC(__asm_invalidate_icache_all)
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