mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
89 lines
1.8 KiB
C
89 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*/
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#include <common.h>
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#include <env.h>
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#include <init.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/global_data.h>
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#include <asm/arch-imx9/ccm_regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-imx9/imx93_pins.h>
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#include <asm/arch/clock.h>
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#include <power/pmic.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static iomux_v3_cfg_t const uart_pads[] = {
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MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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init_uart_clk(LPUART1_CLK_ROOT);
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return 0;
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}
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static int setup_fec(void)
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{
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return set_clk_enet(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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static int setup_eqos(void)
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{
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struct blk_ctrl_wakeupmix_regs *bctrl =
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(struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&bctrl->eqos_gpr,
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BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
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BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
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return set_clk_eqos(ENET_125MHZ);
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}
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int board_init(void)
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{
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if (CONFIG_IS_ENABLED(FEC_MXC))
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setup_fec();
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if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
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setup_eqos();
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return 0;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_IS_IN_MMC
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board_late_mmc_env_init();
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#endif
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_name", "11X11_EVK");
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env_set("board_rev", "iMX93");
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#endif
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return 0;
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}
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