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u-boot/arch/arm/include/asm/arch-aspeed
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Joel Stanley 4080714f5e clk: ast2600: Add YCLK control for HACE 
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
..
boot0.h aspeed: Add AST2600 platform support 2021-01-18 15:23:06 -05:00
pinctrl.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
platform.h aspeed: ast2600: Enlarge SRAM size 2021-11-17 17:04:59 -05:00
scu_ast2500.h clk: aspeed: Add support for SD clock 2019-09-05 15:27:31 +08:00
scu_ast2600.h clk: ast2600: Add YCLK control for HACE 2021-11-17 17:05:00 -05:00
sdram_ast2500.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
sdram_ast2600.h ram: aspeed: Add AST2600 DRAM control support 2021-01-18 15:19:15 -05:00
timer.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wdt.h watchdog: aspeed: restore default value of reset_mask 2018-10-22 09:18:49 -04:00
wdt_ast2600.h wdt: aspeed: Add AST2600 watchdog support 2021-01-18 15:23:05 -05:00