mirror of
https://github.com/AsahiLinux/u-boot
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ee31be429b
The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
102 lines
2.8 KiB
C
102 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef CPS_DRV_H_
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#define CPS_DRV_H_
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#ifdef DEMO_TB
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#include <cdn_demo.h>
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#else
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#include <asm/io.h>
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#endif
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#define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg)))
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#define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value)))
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#define CPS_FLD_MASK(fld) (fld ## _MASK)
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#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
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#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
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#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
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#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
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#define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_SHIFT(fld)), \
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(u32)(reg_value)))
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#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_SHIFT(fld)), \
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(u32)(reg_value), (u32)(value)))
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#define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \
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(u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_WOCLR(fld)), \
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(u32)(reg_value)))
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#ifdef CLR_USED
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#define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \
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(u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_WOSET(fld)), \
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(u32)(CPS_FLD_WOCLR(fld)), \
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(u32)(reg_value)))
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#endif
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static inline u32 cps_regread(volatile u32 *reg);
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static inline u32 cps_regread(volatile u32 *reg)
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{
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return readl(reg);
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}
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static inline void cps_regwrite(volatile u32 *reg, u32 value);
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static inline void cps_regwrite(volatile u32 *reg, u32 value)
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{
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writel(value, reg);
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}
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static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
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static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value)
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{
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u32 result = (reg_value & mask) >> shift;
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return result;
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}
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static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value);
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static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value)
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{
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u32 new_value = (value << shift) & mask;
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new_value = (reg_value & ~mask) | new_value;
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return new_value;
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}
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static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
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static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value)
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{
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u32 new_value = reg_value;
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if ((width == 1U) && (is_woclr == 0U))
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new_value |= mask;
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return new_value;
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}
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#ifdef CLR_USED
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static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
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static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value)
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{
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u32 new_value = reg_value;
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if ((width == 1U) && (is_woset == 0U))
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new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
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return new_value;
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}
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#endif /* CLR_USED */
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#endif /* CPS_DRV_H_ */
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